fd.tan.rpt

这是一个键盘防抖动的C程序。该防抖动程序采用计数器型

+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Sun May 06 09:34:43 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off fd -c fd
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "q[14]" as buffer
Info: Clock "clk" has Internal fmax of 47.62 MHz between source register "q[0]" and destination register "q[16]" (period= 21.0 ns)
    Info: + Longest register to register delay is 16.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 35; REG Node = 'q[0]'
        Info: 2: + IC(2.000 ns) + CELL(8.000 ns) = 10.000 ns; Loc. = SEXP1; Fanout = 8; COMB Node = 'reduce_nor~4sexp'
        Info: 3: + IC(0.000 ns) + CELL(6.000 ns) = 16.000 ns; Loc. = LC8; Fanout = 19; REG Node = 'q[16]'
        Info: Total cell delay = 14.000 ns ( 87.50 % )
        Info: Total interconnect delay = 2.000 ns ( 12.50 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 10.000 ns
            Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_6; Fanout = 25; CLK Node = 'clk'
            Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC8; Fanout = 19; REG Node = 'q[16]'
            Info: Total cell delay = 8.000 ns ( 80.00 % )
            Info: Total interconnect delay = 2.000 ns ( 20.00 % )
        Info: - Longest clock path from clock "clk" to source register is 10.000 ns
            Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_6; Fanout = 25; CLK Node = 'clk'
            Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC1; Fanout = 35; REG Node = 'q[0]'
            Info: Total cell delay = 8.000 ns ( 80.00 % )
            Info: Total interconnect delay = 2.000 ns ( 20.00 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Micro setup delay of destination is 4.000 ns
Info: tsu for register "lpm_counter:jsq_rtl_0|dffs[2]" (data pin = "key", clock pin = "clk") is -4.000 ns
    Info: + Longest pin to register delay is 11.000 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_4; Fanout = 16; PIN Node = 'key'
        Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC17; Fanout = 1; COMB Node = 'lpm_counter:jsq_rtl_0|dffs[2]~195'
        Info: 3: + IC(0.000 ns) + CELL(1.000 ns) = 11.000 ns; Loc. = LC18; Fanout = 11; REG Node = 'lpm_counter:jsq_rtl_0|dffs[2]'
        Info: Total cell delay = 9.000 ns ( 81.82 % )
        Info: Total interconnect delay = 2.000 ns ( 18.18 % )
    Info: + Micro setup delay of destination is 4.000 ns
    Info: - Shortest clock path from clock "clk" to destination register is 19.000 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_6; Fanout = 25; CLK Node = 'clk'
        Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 11.000 ns; Loc. = LC3; Fanout = 27; REG Node = 'q[14]'
        Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 19.000 ns; Loc. = LC18; Fanout = 11; REG Node = 'lpm_counter:jsq_rtl_0|dffs[2]'
        Info: Total cell delay = 15.000 ns ( 78.95 % )
        Info: Total interconnect delay = 4.000 ns ( 21.05 % )
Info: tco from clock "clk" to destination pin "keyout" through register "lpm_counter:jsq_rtl_0|dffs[0]" is 33.000 ns
    Info: + Longest clock path from clock "clk" to source register is 19.000 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_6; Fanout = 25; CLK Node = 'clk'
        Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 11.000 ns; Loc. = LC3; Fanout = 27; REG Node = 'q[14]'
        Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 19.000 ns; Loc. = LC32; Fanout = 11; REG Node = 'lpm_counter:jsq_rtl_0|dffs[0]'
        Info: Total cell delay = 15.000 ns ( 78.95 % )
        Info: Total interconnect delay = 4.000 ns ( 21.05 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Longest register to pin delay is 13.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC32; Fanout = 11; REG Node = 'lpm_counter:jsq_rtl_0|dffs[0]'
        Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 9.000 ns; Loc. = LC19; Fanout = 1; COMB Node = 'reduce_nor~6'
        Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 13.000 ns; Loc. = PIN_21; Fanout = 0; PIN Node = 'keyout'
        Info: Total cell delay = 11.000 ns ( 84.62 % )
        Info: Total interconnect delay = 2.000 ns ( 15.38 % )
Info: th for register "lpm_counter:jsq_rtl_0|dffs[0]" (data pin = "key", clock pin = "clk") is 13.000 ns
    Info: + Longest clock path from clock "clk" to destination register is 19.000 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_6; Fanout = 25; CLK Node = 'clk'
        Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 11.000 ns; Loc. = LC3; Fanout = 27; REG Node = 'q[14]'
        Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 19.000 ns; Loc. = LC32; Fanout = 11; REG Node = 'lpm_counter:jsq_rtl_0|dffs[0]'
        Info: Total cell delay = 15.000 ns ( 78.95 % )
        Info: Total interconnect delay = 4.000 ns ( 21.05 % )
    Info: + Micro hold delay of destination is 4.000 ns
    Info: - Shortest pin to register delay is 10.000 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_4; Fanout = 16; PIN Node = 'key'
        Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC32; Fanout = 11; REG Node = 'lpm_counter:jsq_rtl_0|dffs[0]'
        Info: Total cell delay = 8.000 ns ( 80.00 % )
        Info: Total interconnect delay = 2.000 ns ( 20.00 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Sun May 06 09:34:44 2007
    Info: Elapsed time: 00:00:01