_primary.vhd

来自「ASIC 设计中 包存储功能的fifo」· VHDL 代码 · 共 17 行

library verilog;
use verilog.vl_types.all;
entity bench is
    port(
        clk             : out    vl_logic;
        rst             : out    vl_logic;
        val             : out    vl_logic;
        sop             : out    vl_logic;
        eop             : out    vl_logic;
        err             : out    vl_logic;
        \mod\           : out    vl_logic_vector(1 downto 0);
        full            : out    vl_logic;
        len_en          : out    vl_logic;
        dout            : out    vl_logic_vector(31 downto 0)
    );
end bench;