_primary.vhd

来自「ASIC 设计中 包存储功能的fifo」· VHDL 代码 · 共 17 行

library verilog;
use verilog.vl_types.all;
entity write is
    port(
        clk             : in     vl_logic;
        rst             : in     vl_logic;
        wea             : in     vl_logic;
        enb             : in     vl_logic;
        eop             : in     vl_logic;
        eopo            : in     vl_logic;
        err             : in     vl_logic;
        full            : out    vl_logic;
        empty           : out    vl_logic;
        p_empty         : out    vl_logic
    );
end write;