top.txt

用verilog实现了IIC接口与EEPROM存储器的接口设计

//模块功能：用于把产生测试信号的模块（Signal）与设计的具体模块（EEPROM_WR）
//以及EEPROM虚拟模块连接起来的模块，用于关于全面测试

`timescale 1ns/1ns
`include "./Signal.v"
`include "./EEPROM.v"
`include "./EEPROM_WR.v"

module Top;

    wire RESET;
    wire CLK;
    wire RD,WR;
    wire ACK;
    wire[10:0] ADDR;
    wire[7:0] DATA;
    wire SCL;
    wire SDA;
    Signal signal(.RESET(RESET),.CLK(CLK),.RD(RD),.WR(WR),.ADDR(ADDR),.ACK(ACK),.DATA(DATA));
    EEPROM_WR eeprom_wr(.RESET(RESET),.SDA(SDA),.SCL(SCL),.ACK(ACK),.CLK(CLK),.WR(WR),.RD(RD),.ADDR(ADDR),.DATA(DATA));
    EEPROM eeprom(.sda(SDA),.scl(SCL));

endmodule