signal.v

用verilog实现了IIC接口与EEPROM存储器的接口设计

`timescale 1ns/1ns
`define timeslice 200
module Signal(RESET,CLK,RD,WR,ADDR,ACK,DATA);
    output RESET;     //????
    output CLK;       //????
    output RD,WR;      //????
    output[10:0] ADDR;     // 11?????
    input ACK;         //?????????
    input[7:0] DATA;  // ???
    reg RESET;
    reg CLK;
    reg RD,WR;
    reg W_R;         //?????????????
    reg[10:0] ADDR;
    reg[7:0] data_to_eeprom;
    reg[10:0] addr_mem[0:255];
    reg[7:0] data_mem[0:255];
    reg[7:0] ROM[0:2047];
    integer i,j;
    integer OUTFILE;
    assign DATA=(W_R)?8'bz:data_to_eeprom;
    
    //-----------??????---------------------
    always #(`timeslice/2)
    CLK=~CLK;
    
    
    //-----------??????---------------------
    initial
       begin
           RESET=1;
           i=0;
           j=0;
           W_R=0;
           CLK=0;
           RD=0;
           WR=0;
           #1000;
           RESET=0;
           repeat(15)   //???15??????????????????????
           begin
               #(5*`timeslice);
               WR=1;
               #(`timeslice);
               WR=0;
               @(posedge ACK);   //EEPROM_WR?????????
           end
           #(10*`timeslice)
           W_R=1;         //?????
           repeat(15)      //???15???
           begin
               #(5*`timeslice);
               RD=1;
               #(`timeslice);
               RD=0;
               @(posedge ACK);      //EEPROM_WR?????????
           end
       end
  
       
        
    
    //----------???--------------------------
    initial
    begin
        $display("writing----writing----writing----writing");
        #(2*`timeslice);
        for(i=0;i<=15;i=i+1)
           begin
               ADDR=addr_mem[i];            //????????
               data_to_eeprom=data_mem[i];   //???????????
               $fdisplay(OUTFILE,"@%0h   %0h",ADDR,data_to_eeprom);
               //?????????????????eeprom.dat???
               @(posedge ACK)  ;    //EEPROM_WR?????????
           end
       end
       
    
    //----------???---------------------------
    initial
    @(posedge W_R)
    begin
        ADDR=addr_mem[0];
        $fclose(OUTFILE);      //???????eeprom.dat??
        $readmemh("./eeprom.dat",ROM);      //??????????ROM?
        $display("Begin READING----READING----READING----READING----");
        for(j=0;j<=15;j=j+1)
        begin
            ADDR=addr_mem[j];
            @(posedge ACK);
            if(DATA==ROM[ADDR])      //?????????????????????
            $display("DATA%0h==ROM[%0h]---read right",DATA,ADDR);
            else
            $display("DATA%0h!=ROM[%0h]---read wrong",DATA,ADDR);
        end
    end
    
    initial
    begin
        OUTFILE=$fopen("./eeprom.dat");      //??????eeprom.dat?????
        $readmemh("./addr.dat",addr_mem);      //?????????????
        $readmemh("./data.dat",data_mem);      //?????EEPROM??????????
    end
    
endmodule