eeprom_wr.txt

用verilog实现了IIC接口与EEPROM存储器的接口设计

            else
               begin
                   ACK<=1;
                   FF<=0;
                   main_state<=Ackn;
               end
        Ackn:
           begin
               ACK<=0;
               WF<=0;
               RF<=0;
               main_state<=Idle;
           end
        default:main_state<=Idle;
endcase
end
                
                  

//-------串行数据转换为并行数据任务------------
task shift8in;
    begin
        casex(sh8in_state)
            sh8in_begin:
               sh8in_state<=sh8in_bit7;
            sh8in_bit7:if(SCL)
                           begin
                               data_from_rm[7]<=SDA;
                               sh8in_state<=sh8in_bit6;
                           end
                        else
                           sh8in_state<=sh8in_bit7;
            sh8in_bit6:if(SCL)
                           begin
                               data_from_rm[6]<=SDA;
                               sh8in_state<=sh8in_bit5;
                           end
                        else
                           sh8in_state<=sh8in_bit6;
            sh8in_bit5:if(SCL)
                           begin
                               data_from_rm[5]<=SDA;
                               sh8in_state<=sh8in_bit4;
                           end
                        else
                           sh8in_state<=sh8in_bit5;
            sh8in_bit4:if(SCL)
                           begin
                               data_from_rm[4]<=SDA;
                               sh8in_state<=sh8in_bit3;
                           end
                        else
                           sh8in_state<=sh8in_bit4;                           
            sh8in_bit3:if(SCL)
                           begin
                               data_from_rm[3]<=SDA;
                               sh8in_state<=sh8in_bit2;
                           end
                        else
                           sh8in_state<=sh8in_bit3;
            sh8in_bit2:if(SCL)
                           begin
                               data_from_rm[2]<=SDA;
                               sh8in_state<=sh8in_bit1;
                           end
                        else
                           sh8in_state<=sh8in_bit2;
            sh8in_bit1:if(SCL)
                           begin
                               data_from_rm[1]<=SDA;
                               sh8in_state<=sh8in_bit0;
                           end
                        else
                           sh8in_state<=sh8in_bit1;
            sh8in_bit0:if(SCL)
                           begin
                               data_from_rm[0]<=SDA;
                               sh8in_state<=sh8in_end;
                           end
                        else
                           sh8in_state<=sh8in_bit0;
            sh8in_end:if(SCL)
                           begin
                               link_read<=YES;
                               FF<=1;
                               sh8in_state<=sh8in_bit7;
                           end
                        else
                           sh8in_state<=sh8in_end;
            default:begin
                        link_read<=NO;
                        sh8in_state<=sh8in_bit7;
                    end
                   endcase
               end
       endtask

                           
//-------并行数据转换为串行数据任务-----------
task shift8_out;
    begin
        casex(sh8out_state)
            sh8out_bit7:
                        if(!SCL)
                           begin
                               link_sda<=YES;
                               link_write<=YES;
                               sh8out_state<=sh8out_bit6;
                           end
                        else
                           sh8out_state<=sh8out_bit7;
            sh8out_bit6:
                        if(!SCL)
                           begin
                               link_sda<=YES;
                               link_write<=YES;
                               sh8out_state<=sh8out_bit5;
                               sh8out_buf<=sh8out_buf<<1;
                           end
                        else
                           sh8out_state<=sh8out_bit6;
            sh8out_bit5:
               if(!SCL)
                  begin
                      sh8out_state<=sh8out_bit4;
                      sh8out_buf<=sh8out_buf<<1;
                  end
                else
                     sh8out_state<=sh8out_bit5;
            sh8out_bit4:
               if(!SCL)
                  begin
                      sh8out_state<=sh8out_bit3;
                      sh8out_buf<=sh8out_buf<<1;
                  end
                else
                     sh8out_state<=sh8out_bit4;                        
            sh8out_bit3:
               if(!SCL)
                  begin
                      sh8out_state<=sh8out_bit2;
                      sh8out_buf<=sh8out_buf<<1;
                  end
                else
                     sh8out_state<=sh8out_bit3;
            sh8out_bit2:
               if(!SCL)
                  begin
                      sh8out_state<=sh8out_bit1;
                      sh8out_buf<=sh8out_buf<<1;
                  end
                else
                     sh8out_state<=sh8out_bit2;
            sh8out_bit1:
               if(!SCL)
                  begin
                      sh8out_state<=sh8out_bit0;
                      sh8out_buf<=sh8out_buf<<1;
                  end
                else
                     sh8out_state<=sh8out_bit3;
            sh8out_bit0:
               if(!SCL)
                  begin
                      sh8out_state<=sh8out_end;
                      sh8out_buf<=sh8out_buf<<1;
                  end
                else
                     sh8out_state<=sh8out_bit0;
            sh8out_end:
               if(!SCL)
                  begin
                      link_sda<=NO;
                      link_write<=NO;
                      FF<=1;
                  end
                else
                   sh8out_state<=sh8out_end;
           endcase
       end
   endtask



//-------输出启动信号任务-----------
task shift_head;
    begin
        casex(head_state)
            head_begin:
            if(!SCL)
               begin
                   link_write<=NO;
                   link_sda<=YES;
                   link_head<=YES;
                   head_state<=head_bit;
               end
               else
               head_state<=head_begin;
            
            head_bit:
               if(SCL)
               begin
                   FF<=1;
                   head_buf<=head_buf<<1;
                   head_state<=head_end;
               end
               else
               head_state<=head_end;
       endcase
   end
   endtask
                   



//-------输出停止信号任务------------
task shift_stop;
    begin
        casex(stop_state)
            stop_begin:
               if(!SCL)
               begin
                   link_sda<=YES;
                   link_write<=NO;
                   link_stop<=YES;
                   stop_state<=stop_bit;
               end
               else
               stop_state<=stop_begin;
               stop_bit:
               if(SCL)
               begin
                    stop_buf<=stop_buf<<1;
                    stop_state<=stop_end;
                end
                else
                stop_state<=stop_bit;
                stop_end:
                if(!SCL)
                begin
                    link_head<=NO;
                    link_stop<=NO;
                    link_sda<=NO;
                    FF<=1;
                end
                else
                   stop_state<=stop_end;
           endcase
       end
   endtask
   endmodule