szz.twr

VHDL设计的数字时钟

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Release 6.3i Trace G.38
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

D:/Xilinx/bin/nt/trce.exe -intstyle ise -e 3 -l 3 -xml szz szz.ncd -o szz.twr
szz.pcf


Design file:              szz.ncd
Physical constraint file: szz.pcf
Device,speed:             xc3s200,-4 (PRODUCTION 1.35 2004-11-11)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock md3
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  |  Clock |
Source      | clk (edge) | clk (edge) |Internal Clock(s) |  Phase |
------------+------------+------------+------------------+--------+
md1         |    8.973(F)|    2.197(F)|_n0054            |   0.000|
------------+------------+------------+------------------+--------+

Clock md3 to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
dout<0>     |   10.721(F)|_n0054            |   0.000|
dout<1>     |   10.721(F)|_n0054            |   0.000|
dout<2>     |   10.383(F)|_n0054            |   0.000|
dout<3>     |   10.746(F)|_n0054            |   0.000|
dout<4>     |   10.746(F)|_n0054            |   0.000|
dout<5>     |   11.090(F)|_n0054            |   0.000|
dout<6>     |   11.090(F)|_n0054            |   0.000|
dout<7>     |   10.383(F)|_n0054            |   0.000|
selout<0>   |   12.117(F)|_n0054            |   0.000|
selout<1>   |   11.598(F)|_n0054            |   0.000|
selout<2>   |   11.598(F)|_n0054            |   0.000|
selout<3>   |   11.477(F)|_n0054            |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock inclk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
inclk          |    7.713|         |         |         |
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock md3
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
md3            |         |         |    6.497|    6.497|
---------------+---------+---------+---------+---------+

Analysis completed Fri Nov 03 16:24:07 2006
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Peak Memory Usage: 55 MB