szz_map_fpga_editor.log

VHDL设计的数字时钟

#:C0     
#Xilinx FPGA Editor Command Log File
#Editor Version:
#:V   NT M2.1 1.0
#Design Path Name:
#:N   szz_map.ncd
#Current Working Directory:
#:D   D:\Xilinx\bin\200404015010
#Part Type:
#:P  Xilinx xc3s200 pq208 -4
#Date/Time:
#:T   Fri Nov 03 13:50:35 2006
#------------------------------
	#1
setattr main edit-mode no-logic-changes