📄 test.map.rpt
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; Total registers ; 58 ;
; Total logic cells in carry chains ; 49 ;
; I/O pins ; 6 ;
; Maximum fan-out node ; clk ;
; Maximum fan-out ; 46 ;
; Total fan-out ; 546 ;
; Average fan-out ; 3.19 ;
+---------------------------------------------+-------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |test ; 165 (1) ; 58 ; 0 ; 6 ; 0 ; 107 (1) ; 15 (0) ; 43 (0) ; 49 (0) ; 0 (0) ; |test ;
; |ClkUnit:inst1| ; 19 (19) ; 11 ; 0 ; 0 ; 0 ; 8 (8) ; 1 (1) ; 10 (10) ; 0 (0) ; 0 (0) ; |test|ClkUnit:inst1 ;
; |PWM:inst3| ; 48 (48) ; 8 ; 0 ; 0 ; 0 ; 40 (40) ; 1 (1) ; 7 (7) ; 34 (34) ; 0 (0) ; |test|PWM:inst3 ;
; |PWM:inst4| ; 29 (29) ; 12 ; 0 ; 0 ; 0 ; 17 (17) ; 9 (9) ; 3 (3) ; 15 (15) ; 0 (0) ; |test|PWM:inst4 ;
; |RxUnit:inst| ; 52 (52) ; 27 ; 0 ; 0 ; 0 ; 25 (25) ; 4 (4) ; 23 (23) ; 0 (0) ; 0 (0) ; |test|RxUnit:inst ;
; |SEL:inst2| ; 16 (16) ; 0 ; 0 ; 0 ; 0 ; 16 (16) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |test|SEL:inst2 ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+----------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches ;
+-----------------------------------------------------+---------------------+------------------------+
; Latch Name ; Latch Enable Signal ; Free of Timing Hazards ;
+-----------------------------------------------------+---------------------+------------------------+
; SEL:inst2|Servo_Width_Ctr[6] ; SEL:inst2|comb~1 ; yes ;
; SEL:inst2|Motor_Width_Ctr[6] ; SEL:inst2|comb~0 ; yes ;
; SEL:inst2|Servo_Width_Ctr[5] ; SEL:inst2|comb~1 ; yes ;
; SEL:inst2|Motor_Width_Ctr[5] ; SEL:inst2|comb~0 ; yes ;
; SEL:inst2|Servo_Width_Ctr[4] ; SEL:inst2|comb~1 ; yes ;
; SEL:inst2|Motor_Width_Ctr[4] ; SEL:inst2|comb~0 ; yes ;
; SEL:inst2|Servo_Width_Ctr[3] ; SEL:inst2|comb~1 ; yes ;
; SEL:inst2|Motor_Width_Ctr[3] ; SEL:inst2|comb~0 ; yes ;
; SEL:inst2|Servo_Width_Ctr[2] ; SEL:inst2|comb~1 ; yes ;
; SEL:inst2|Servo_Width_Ctr[1] ; SEL:inst2|comb~1 ; yes ;
; SEL:inst2|Motor_Width_Ctr[2] ; SEL:inst2|comb~0 ; yes ;
; SEL:inst2|Motor_Width_Ctr[1] ; SEL:inst2|comb~0 ; yes ;
; SEL:inst2|Servo_Width_Ctr[0] ; SEL:inst2|comb~1 ; yes ;
; SEL:inst2|Motor_Width_Ctr[0] ; SEL:inst2|comb~0 ; yes ;
; Number of user-specified and inferred latches = 14 ; ; ;
+-----------------------------------------------------+---------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 58 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 16 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------+
; 3:1 ; 5 bits ; 10 LEs ; 5 LEs ; 5 LEs ; Yes ; |test|ClkUnit:inst1|\DivClk26:Cnt26[2] ;
; 7:1 ; 2 bits ; 8 LEs ; 2 LEs ; 6 LEs ; Yes ; |test|RxUnit:inst|DOut[6] ;
; 7:1 ; 6 bits ; 24 LEs ; 6 LEs ; 18 LEs ; Yes ; |test|RxUnit:inst|DOut[5] ;
; 9:1 ; 8 bits ; 48 LEs ; 8 LEs ; 40 LEs ; Yes ; |test|RxUnit:inst|ShtReg[4] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Tue Oct 09 10:48:33 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off test -c test
Info: Found 2 design units, including 1 entities, in source file PWM.vhd
Info: Found design unit 1: PWM-arch
Info: Found entity 1: PWM
Info: Found 2 design units, including 1 entities, in source file SEL.vhd
Info: Found design unit 1: SEL-Behaviour
Info: Found entity 1: SEL
Info: Found 2 design units, including 1 entities, in source file clkUnit.vhd
Info: Found design unit 1: ClkUnit-Behaviour
Info: Found entity 1: ClkUnit
Info: Found 2 design units, including 1 entities, in source file RxUnit.vhd
Info: Found design unit 1: RxUnit-Behaviour
Info: Found entity 1: RxUnit
Info: Found 1 design units, including 1 entities, in source file test.bdf
Info: Found entity 1: test
Info: Found 2 design units, including 0 entities, in source file uart_lib.vhd
Info: Found design unit 1: UART_Def
Info: Found design unit 2: UART_Def-body
Info: Elaborating entity "test" for the top level hierarchy
Info: Elaborating entity "PWM" for hierarchy "PWM:inst4"
Warning (10492): VHDL Process Statement warning at PWM.vhd(68): signal "width_word" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Elaborating entity "SEL" for hierarchy "SEL:inst2"
Warning (10492): VHDL Process Statement warning at SEL.vhd(33): signal "RBuffer" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at SEL.vhd(34): signal "RBuffer" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at SEL.vhd(35): signal "RBuffer" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10631): VHDL Process Statement warning at SEL.vhd(27): inferring latch(es) for signal or variable "Servo_Width_Ctr", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at SEL.vhd(27): inferring latch(es) for signal or variable "Motor_Width_Ctr", which holds its previous value in one or more paths through the process
Info (10041): Verilog HDL or VHDL info at SEL.vhd(27): inferred latch for "Motor_Width_Ctr[0]"
Info (10041): Verilog HDL or VHDL info at SEL.vhd(27): inferred latch for "Motor_Width_Ctr[1]"
Info (10041): Verilog HDL or VHDL info at SEL.vhd(27): inferred latch for "Motor_Width_Ctr[2]"
Info (10041): Verilog HDL or VHDL info at SEL.vhd(27): inferred latch for "Motor_Width_Ctr[3]"
Info (10041): Verilog HDL or VHDL info at SEL.vhd(27): inferred latch for "Motor_Width_Ctr[4]"
Info (10041): Verilog HDL or VHDL info at SEL.vhd(27): inferred latch for "Motor_Width_Ctr[5]"
Info (10041): Verilog HDL or VHDL info at SEL.vhd(27): inferred latch for "Motor_Width_Ctr[6]"
Info (10041): Verilog HDL or VHDL info at SEL.vhd(27): inferred latch for "Servo_Width_Ctr[0]"
Info (10041): Verilog HDL or VHDL info at SEL.vhd(27): inferred latch for "Servo_Width_Ctr[1]"
Info (10041): Verilog HDL or VHDL info at SEL.vhd(27): inferred latch for "Servo_Width_Ctr[2]"
Info (10041): Verilog HDL or VHDL info at SEL.vhd(27): inferred latch for "Servo_Width_Ctr[3]"
Info (10041): Verilog HDL or VHDL info at SEL.vhd(27): inferred latch for "Servo_Width_Ctr[4]"
Info (10041): Verilog HDL or VHDL info at SEL.vhd(27): inferred latch for "Servo_Width_Ctr[5]"
Info (10041): Verilog HDL or VHDL info at SEL.vhd(27): inferred latch for "Servo_Width_Ctr[6]"
Info: Elaborating entity "RxUnit" for hierarchy "RxUnit:inst"
Info: Elaborating entity "ClkUnit" for hierarchy "ClkUnit:inst1"
Info: Duplicate registers merged to single register
Info: Duplicate register "PWM:inst4|clk_servo" merged to single register "PWM:inst3|clk_servo"
Info: Duplicate registers merged to single register
Info: Duplicate register "PWM:inst3|div_reg_pwm[11]" merged to single register "PWM:inst4|div_reg_pwm[11]"
Info: Duplicate register "PWM:inst3|div_reg_pwm[10]" merged to single register "PWM:inst4|div_reg_pwm[10]"
Info: Duplicate register "PWM:inst3|div_reg_pwm[9]" merged to single register "PWM:inst4|div_reg_pwm[9]"
Info: Duplicate register "PWM:inst3|div_reg_pwm[8]" merged to single register "PWM:inst4|div_reg_pwm[8]"
Info: Duplicate register "PWM:inst3|div_reg_pwm[0]" merged to single register "PWM:inst4|div_reg_pwm[0]"
Info: Duplicate register "PWM:inst3|div_reg_pwm[1]" merged to single register "PWM:inst4|div_reg_pwm[1]"
Info: Duplicate register "PWM:inst3|div_reg_pwm[2]" merged to single register "PWM:inst4|div_reg_pwm[2]"
Info: Duplicate register "PWM:inst3|div_reg_pwm[3]" merged to single register "PWM:inst4|div_reg_pwm[3]"
Info: Duplicate register "PWM:inst3|div_reg_pwm[4]" merged to single register "PWM:inst4|div_reg_pwm[4]"
Info: Duplicate register "PWM:inst3|div_reg_pwm[5]" merged to single register "PWM:inst4|div_reg_pwm[5]"
Info: Duplicate register "PWM:inst3|div_reg_pwm[6]" merged to single register "PWM:inst4|div_reg_pwm[6]"
Info: Duplicate register "PWM:inst3|div_reg_pwm[7]" merged to single register "PWM:inst4|div_reg_pwm[7]"
Info: Implemented 171 device resources after synthesis - the final resource count might be different
Info: Implemented 4 input pins
Info: Implemented 2 output pins
Info: Implemented 165 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 6 warnings
Info: Processing ended: Tue Oct 09 10:48:36 2007
Info: Elapsed time: 00:00:03
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