test.hier_info

两路电机CPLD控制,串口通信

|test
to_motor <= PWM:inst4.to_servo
clk => PWM:inst4.clk
clk => RxUnit:inst.Clk
clk => ClkUnit:inst1.SysClk
clk => PWM:inst3.clk
rst => inst7.IN0
remote => inst7.IN1
rxd => RxUnit:inst.RxD
to_servo <= PWM:inst3.to_servo


|test|PWM:inst4
clk => clk_servo.CLK
clk => div_reg[0].CLK
clk => div_reg[1].CLK
clk => div_reg[2].CLK
clk => div_reg[3].CLK
clk => div_reg[4].CLK
clk => div_reg[5].CLK
clk => div_reg[6].CLK
width_word[0] => LessThan0.IN5
width_word[1] => Add2.IN2
width_word[2] => Add2.IN6
width_word[3] => Add2.IN5
width_word[4] => Add2.IN1
width_word[5] => Add2.IN0
width_word[6] => Add2.IN4
to_servo <= LessThan0.DB_MAX_OUTPUT_PORT_TYPE


|test|SEL:inst2
RBuffer[0] => Servo_Width_Ctr[0]$latch.DATAIN
RBuffer[0] => Motor_Width_Ctr[0]$latch.DATAIN
RBuffer[1] => Servo_Width_Ctr[1]$latch.DATAIN
RBuffer[1] => Motor_Width_Ctr[1]$latch.DATAIN
RBuffer[2] => Servo_Width_Ctr[2]$latch.DATAIN
RBuffer[2] => Motor_Width_Ctr[2]$latch.DATAIN
RBuffer[3] => Servo_Width_Ctr[3]$latch.DATAIN
RBuffer[3] => Motor_Width_Ctr[3]$latch.DATAIN
RBuffer[4] => Servo_Width_Ctr[4]$latch.DATAIN
RBuffer[4] => Motor_Width_Ctr[4]$latch.DATAIN
RBuffer[5] => Servo_Width_Ctr[5]$latch.DATAIN
RBuffer[5] => Motor_Width_Ctr[5]$latch.DATAIN
RBuffer[6] => Servo_Width_Ctr[6]$latch.DATAIN
RBuffer[6] => Motor_Width_Ctr[6]$latch.DATAIN
RBuffer[7] => comb~1.IN0
RBuffer[7] => comb~0.IN0
DReady => comb~0.IN1
DReady => comb~1.IN1
Rst => Motor_Width_Ctr[0]$latch.PRESET
Rst => Motor_Width_Ctr[1]$latch.PRESET
Rst => Motor_Width_Ctr[2]$latch.PRESET
Rst => Motor_Width_Ctr[3]$latch.PRESET
Rst => Motor_Width_Ctr[4]$latch.PRESET
Rst => Motor_Width_Ctr[5]$latch.PRESET
Rst => Motor_Width_Ctr[6]$latch.ACLR
Rst => Servo_Width_Ctr[0]$latch.PRESET
Rst => Servo_Width_Ctr[1]$latch.PRESET
Rst => Servo_Width_Ctr[2]$latch.PRESET
Rst => Servo_Width_Ctr[3]$latch.PRESET
Rst => Servo_Width_Ctr[4]$latch.PRESET
Rst => Servo_Width_Ctr[5]$latch.PRESET
Rst => Servo_Width_Ctr[6]$latch.ACLR
Servo_Width_Ctr[0] <= Servo_Width_Ctr[0]$latch.DB_MAX_OUTPUT_PORT_TYPE
Servo_Width_Ctr[1] <= Servo_Width_Ctr[1]$latch.DB_MAX_OUTPUT_PORT_TYPE
Servo_Width_Ctr[2] <= Servo_Width_Ctr[2]$latch.DB_MAX_OUTPUT_PORT_TYPE
Servo_Width_Ctr[3] <= Servo_Width_Ctr[3]$latch.DB_MAX_OUTPUT_PORT_TYPE
Servo_Width_Ctr[4] <= Servo_Width_Ctr[4]$latch.DB_MAX_OUTPUT_PORT_TYPE
Servo_Width_Ctr[5] <= Servo_Width_Ctr[5]$latch.DB_MAX_OUTPUT_PORT_TYPE
Servo_Width_Ctr[6] <= Servo_Width_Ctr[6]$latch.DB_MAX_OUTPUT_PORT_TYPE
Motor_Width_Ctr[0] <= Motor_Width_Ctr[0]$latch.DB_MAX_OUTPUT_PORT_TYPE
Motor_Width_Ctr[1] <= Motor_Width_Ctr[1]$latch.DB_MAX_OUTPUT_PORT_TYPE
Motor_Width_Ctr[2] <= Motor_Width_Ctr[2]$latch.DB_MAX_OUTPUT_PORT_TYPE
Motor_Width_Ctr[3] <= Motor_Width_Ctr[3]$latch.DB_MAX_OUTPUT_PORT_TYPE
Motor_Width_Ctr[4] <= Motor_Width_Ctr[4]$latch.DB_MAX_OUTPUT_PORT_TYPE
Motor_Width_Ctr[5] <= Motor_Width_Ctr[5]$latch.DB_MAX_OUTPUT_PORT_TYPE
Motor_Width_Ctr[6] <= Motor_Width_Ctr[6]$latch.DB_MAX_OUTPUT_PORT_TYPE


|test|RxUnit:inst
Clk => tmpRxD.CLK
Clk => DOut[0].CLK
Clk => DOut[1].CLK
Clk => DOut[2].CLK
Clk => DOut[3].CLK
Clk => DOut[4].CLK
Clk => DOut[5].CLK
Clk => DOut[6].CLK
Clk => DOut[7].CLK
Clk => ShtReg[0].CLK
Clk => ShtReg[1].CLK
Clk => ShtReg[2].CLK
Clk => ShtReg[3].CLK
Clk => ShtReg[4].CLK
Clk => ShtReg[5].CLK
Clk => ShtReg[6].CLK
Clk => ShtReg[7].CLK
Clk => outErr.CLK
Clk => frameErr.CLK
Clk => tmpDRdy.CLK
Clk => Start.CLK
Clk => SampleCnt[0].CLK
Clk => SampleCnt[1].CLK
Clk => SampleCnt[2].CLK
Clk => SampleCnt[3].CLK
Clk => BitCnt[0].CLK
Clk => BitCnt[1].CLK
Clk => BitCnt[2].CLK
Clk => BitCnt[3].CLK
Reset => BitCnt~20.OUTPUTSELECT
Reset => BitCnt~21.OUTPUTSELECT
Reset => BitCnt~22.OUTPUTSELECT
Reset => BitCnt~23.OUTPUTSELECT
Reset => SampleCnt~20.OUTPUTSELECT
Reset => SampleCnt~21.OUTPUTSELECT
Reset => SampleCnt~22.OUTPUTSELECT
Reset => SampleCnt~23.OUTPUTSELECT
Reset => Start~6.OUTPUTSELECT
Reset => tmpDRdy~5.OUTPUTSELECT
Reset => frameErr~4.OUTPUTSELECT
Reset => outErr~4.OUTPUTSELECT
Reset => ShtReg~32.OUTPUTSELECT
Reset => ShtReg~33.OUTPUTSELECT
Reset => ShtReg~34.OUTPUTSELECT
Reset => ShtReg~35.OUTPUTSELECT
Reset => ShtReg~36.OUTPUTSELECT
Reset => ShtReg~37.OUTPUTSELECT
Reset => ShtReg~38.OUTPUTSELECT
Reset => ShtReg~39.OUTPUTSELECT
Reset => DOut~32.OUTPUTSELECT
Reset => DOut~33.OUTPUTSELECT
Reset => DOut~34.OUTPUTSELECT
Reset => DOut~35.OUTPUTSELECT
Reset => DOut~36.OUTPUTSELECT
Reset => DOut~37.OUTPUTSELECT
Reset => DOut~38.OUTPUTSELECT
Reset => DOut~39.OUTPUTSELECT
Enable => SampleCnt~16.OUTPUTSELECT
Enable => SampleCnt~17.OUTPUTSELECT
Enable => SampleCnt~18.OUTPUTSELECT
Enable => SampleCnt~19.OUTPUTSELECT
Enable => Start~5.OUTPUTSELECT
Enable => BitCnt~16.OUTPUTSELECT
Enable => BitCnt~17.OUTPUTSELECT
Enable => BitCnt~18.OUTPUTSELECT
Enable => BitCnt~19.OUTPUTSELECT
Enable => ShtReg~24.OUTPUTSELECT
Enable => ShtReg~25.OUTPUTSELECT
Enable => ShtReg~26.OUTPUTSELECT
Enable => ShtReg~27.OUTPUTSELECT
Enable => ShtReg~28.OUTPUTSELECT
Enable => ShtReg~29.OUTPUTSELECT
Enable => ShtReg~30.OUTPUTSELECT
Enable => ShtReg~31.OUTPUTSELECT
Enable => frameErr~3.OUTPUTSELECT
Enable => outErr~3.OUTPUTSELECT
Enable => tmpDRdy~4.OUTPUTSELECT
Enable => DOut~24.OUTPUTSELECT
Enable => DOut~25.OUTPUTSELECT
Enable => DOut~26.OUTPUTSELECT
Enable => DOut~27.OUTPUTSELECT
Enable => DOut~28.OUTPUTSELECT
Enable => DOut~29.OUTPUTSELECT
Enable => DOut~30.OUTPUTSELECT
Enable => DOut~31.OUTPUTSELECT
RxD => SampleCnt~0.OUTPUTSELECT
RxD => SampleCnt~1.OUTPUTSELECT
RxD => SampleCnt~2.OUTPUTSELECT
RxD => SampleCnt~3.OUTPUTSELECT
RxD => Start~0.OUTPUTSELECT
RxD => tmpRxD.DATAIN
RD => tmpDRdy~0.OUTPUTSELECT
FErr <= frameErr.DB_MAX_OUTPUT_PORT_TYPE
OErr <= outErr.DB_MAX_OUTPUT_PORT_TYPE
DRdy <= tmpDRdy.DB_MAX_OUTPUT_PORT_TYPE
DataIn[0] <= DOut[0].DB_MAX_OUTPUT_PORT_TYPE
DataIn[1] <= DOut[1].DB_MAX_OUTPUT_PORT_TYPE
DataIn[2] <= DOut[2].DB_MAX_OUTPUT_PORT_TYPE
DataIn[3] <= DOut[3].DB_MAX_OUTPUT_PORT_TYPE
DataIn[4] <= DOut[4].DB_MAX_OUTPUT_PORT_TYPE
DataIn[5] <= DOut[5].DB_MAX_OUTPUT_PORT_TYPE
DataIn[6] <= DOut[6].DB_MAX_OUTPUT_PORT_TYPE
DataIn[7] <= DOut[7].DB_MAX_OUTPUT_PORT_TYPE


|test|ClkUnit:inst1
SysClk => tmpEnTX.CLK
SysClk => \DivClk16:Cnt16[0].CLK
SysClk => \DivClk16:Cnt16[1].CLK
SysClk => \DivClk16:Cnt16[2].CLK
SysClk => \DivClk16:Cnt16[3].CLK
SysClk => \DivClk16:Cnt16[4].CLK
SysClk => tmpEnRX.CLK
SysClk => \DivClk10:Cnt10[0].CLK
SysClk => \DivClk10:Cnt10[1].CLK
SysClk => \DivClk10:Cnt10[2].CLK
SysClk => \DivClk10:Cnt10[3].CLK
SysClk => ClkDiv26.CLK
SysClk => \DivClk26:Cnt26[0].CLK
SysClk => \DivClk26:Cnt26[1].CLK
SysClk => \DivClk26:Cnt26[2].CLK
SysClk => \DivClk26:Cnt26[3].CLK
SysClk => \DivClk26:Cnt26[4].CLK
EnableRx <= tmpEnRX.DB_MAX_OUTPUT_PORT_TYPE
EnableTx <= tmpEnTX.DB_MAX_OUTPUT_PORT_TYPE
Reset => Cnt10~4.OUTPUTSELECT
Reset => Cnt10~5.OUTPUTSELECT
Reset => Cnt10~6.OUTPUTSELECT
Reset => Cnt10~7.OUTPUTSELECT
Reset => Cnt26~2.OUTPUTSELECT
Reset => Cnt26~1.OUTPUTSELECT
Reset => Cnt26~0.OUTPUTSELECT
Reset => Cnt16~9.OUTPUTSELECT
Reset => Cnt16~8.OUTPUTSELECT
Reset => Cnt16~7.OUTPUTSELECT
Reset => Cnt16~6.OUTPUTSELECT
Reset => Cnt16~5.OUTPUTSELECT
Reset => Cnt26~3.OUTPUTSELECT
Reset => Cnt26~4.OUTPUTSELECT
Reset => ClkDiv26~0.OUTPUTSELECT


|test|PWM:inst3
clk => clk_servo.CLK
clk => div_reg[0].CLK
clk => div_reg[1].CLK
clk => div_reg[2].CLK
clk => div_reg[3].CLK
clk => div_reg[4].CLK
clk => div_reg[5].CLK
clk => div_reg[6].CLK
width_word[0] => LessThan0.IN5
width_word[1] => Add2.IN2
width_word[2] => Add2.IN6
width_word[3] => Add2.IN5
width_word[4] => Add2.IN1
width_word[5] => Add2.IN0
width_word[6] => Add2.IN4
to_servo <= LessThan0.DB_MAX_OUTPUT_PORT_TYPE