test.map.qmsg

两路电机CPLD控制,串口通信

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 09 10:48:33 2007 " "Info: Processing started: Tue Oct 09 10:48:33 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off test -c test " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off test -c test" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "PWM.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file PWM.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 PWM-arch " "Info: Found design unit 1: PWM-arch" {  } { { "PWM.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/PWM.vhd" 27 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 PWM " "Info: Found entity 1: PWM" {  } { { "PWM.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/PWM.vhd" 18 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "SEL.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file SEL.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 SEL-Behaviour " "Info: Found design unit 1: SEL-Behaviour" {  } { { "SEL.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/SEL.vhd" 21 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 SEL " "Info: Found entity 1: SEL" {  } { { "SEL.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/SEL.vhd" 9 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clkUnit.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file clkUnit.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ClkUnit-Behaviour " "Info: Found design unit 1: ClkUnit-Behaviour" {  } { { "clkUnit.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/clkUnit.vhd" 52 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 ClkUnit " "Info: Found entity 1: ClkUnit" {  } { { "clkUnit.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/clkUnit.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "RxUnit.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file RxUnit.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 RxUnit-Behaviour " "Info: Found design unit 1: RxUnit-Behaviour" {  } { { "RxUnit.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/RxUnit.vhd" 58 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 RxUnit " "Info: Found entity 1: RxUnit" {  } { { "RxUnit.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/RxUnit.vhd" 43 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "test.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file test.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 test " "Info: Found entity 1: test" {  } { { "test.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/test.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "uart_lib.vhd 2 0 " "Info: Found 2 design units, including 0 entities, in source file uart_lib.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 UART_Def " "Info: Found design unit 1: UART_Def" {  } { { "uart_lib.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/uart_lib.vhd" 35 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 UART_Def-body " "Info: Found design unit 2: UART_Def-body" {  } { { "uart_lib.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/uart_lib.vhd" 45 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "test " "Info: Elaborating entity \"test\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "PWM PWM:inst4 " "Info: Elaborating entity \"PWM\" for hierarchy \"PWM:inst4\"" {  } { { "test.bdf" "inst4" { Schematic "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/test.bdf" { { 400 336 512 496 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "width_word PWM.vhd(68) " "Warning (10492): VHDL Process Statement warning at PWM.vhd(68): signal \"width_word\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "PWM.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/PWM.vhd" 68 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SEL SEL:inst2 " "Info: Elaborating entity \"SEL\" for hierarchy \"SEL:inst2\"" {  } { { "test.bdf" "inst2" { Schematic "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/test.bdf" { { 96 584 816 192 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "RBuffer SEL.vhd(33) " "Warning (10492): VHDL Process Statement warning at SEL.vhd(33): signal \"RBuffer\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "SEL.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/SEL.vhd" 33 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "RBuffer SEL.vhd(34) " "Warning (10492): VHDL Process Statement warning at SEL.vhd(34): signal \"RBuffer\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "SEL.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/SEL.vhd" 34 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "RBuffer SEL.vhd(35) " "Warning (10492): VHDL Process Statement warning at SEL.vhd(35): signal \"RBuffer\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "SEL.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/SEL.vhd" 35 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "Servo_Width_Ctr SEL.vhd(27) " "Warning (10631): VHDL Process Statement warning at SEL.vhd(27): inferring latch(es) for signal or variable \"Servo_Width_Ctr\", which holds its previous value in one or more paths through the process" {  } { { "SEL.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/SEL.vhd" 27 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "Motor_Width_Ctr SEL.vhd(27) " "Warning (10631): VHDL Process Statement warning at SEL.vhd(27): inferring latch(es) for signal or variable \"Motor_Width_Ctr\", which holds its previous value in one or more paths through the process" {  } { { "SEL.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/SEL.vhd" 27 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "Motor_Width_Ctr\[0\] SEL.vhd(27) " "Info (10041): Verilog HDL or VHDL info at SEL.vhd(27): inferred latch for \"Motor_Width_Ctr\[0\]\"" {  } { { "SEL.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/SEL.vhd" 27 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "Motor_Width_Ctr\[1\] SEL.vhd(27) " "Info (10041): Verilog HDL or VHDL info at SEL.vhd(27): inferred latch for \"Motor_Width_Ctr\[1\]\"" {  } { { "SEL.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/SEL.vhd" 27 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}