test.tan.qmsg

两路电机CPLD控制,串口通信

{ "Info" "ITDB_FULL_TCO_RESULT" "clk to_servo SEL:inst2\|Motor_Width_Ctr\[1\] 27.957 ns register " "Info: tco from clock \"clk\" to destination pin \"to_servo\" through register \"SEL:inst2\|Motor_Width_Ctr\[1\]\" is 27.957 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 15.603 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 15.603 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 46 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 46; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "test.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/test.bdf" { { 24 -24 144 40 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.287 ns) + CELL(1.294 ns) 7.713 ns RxUnit:inst\|DOut\[7\] 2 REG LC_X10_Y7_N7 2 " "Info: 2: + IC(5.287 ns) + CELL(1.294 ns) = 7.713 ns; Loc. = LC_X10_Y7_N7; Fanout = 2; REG Node = 'RxUnit:inst\|DOut\[7\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.581 ns" { clk RxUnit:inst|DOut[7] } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/RxUnit.vhd" 80 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.026 ns) + CELL(0.740 ns) 10.479 ns SEL:inst2\|comb~0 3 COMB LC_X11_Y4_N0 7 " "Info: 3: + IC(2.026 ns) + CELL(0.740 ns) = 10.479 ns; Loc. = LC_X11_Y4_N0; Fanout = 7; COMB Node = 'SEL:inst2\|comb~0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.766 ns" { RxUnit:inst|DOut[7] SEL:inst2|comb~0 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.613 ns) + CELL(0.511 ns) 15.603 ns SEL:inst2\|Motor_Width_Ctr\[1\] 4 REG LC_X12_Y8_N8 4 " "Info: 4: + IC(4.613 ns) + CELL(0.511 ns) = 15.603 ns; Loc. = LC_X12_Y8_N8; Fanout = 4; REG Node = 'SEL:inst2\|Motor_Width_Ctr\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.124 ns" { SEL:inst2|comb~0 SEL:inst2|Motor_Width_Ctr[1] } "NODE_NAME" } } { "SEL.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/SEL.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.677 ns ( 23.57 % ) " "Info: Total cell delay = 3.677 ns ( 23.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "11.926 ns ( 76.43 % ) " "Info: Total interconnect delay = 11.926 ns ( 76.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "15.603 ns" { clk RxUnit:inst|DOut[7] SEL:inst2|comb~0 SEL:inst2|Motor_Width_Ctr[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "15.603 ns" { clk clk~combout RxUnit:inst|DOut[7] SEL:inst2|comb~0 SEL:inst2|Motor_Width_Ctr[1] } { 0.000ns 0.000ns 5.287ns 2.026ns 4.613ns } { 0.000ns 1.132ns 1.294ns 0.740ns 0.511ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "SEL.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/SEL.vhd" 27 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.354 ns + Longest register pin " "Info: + Longest register to pin delay is 12.354 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SEL:inst2\|Motor_Width_Ctr\[1\] 1 REG LC_X12_Y8_N8 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y8_N8; Fanout = 4; REG Node = 'SEL:inst2\|Motor_Width_Ctr\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SEL:inst2|Motor_Width_Ctr[1] } "NODE_NAME" } } { "SEL.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/SEL.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.715 ns) + CELL(0.978 ns) 1.693 ns PWM:inst3\|Add2~129 2 COMB LC_X12_Y8_N1 2 " "Info: 2: + IC(0.715 ns) + CELL(0.978 ns) = 1.693 ns; Loc. = LC_X12_Y8_N1; Fanout = 2; COMB Node = 'PWM:inst3\|Add2~129'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.693 ns" { SEL:inst2|Motor_Width_Ctr[1] PWM:inst3|Add2~129 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1111 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 1.816 ns PWM:inst3\|Add2~127 3 COMB LC_X12_Y8_N2 2 " "Info: 3: + IC(0.000 ns) + CELL(0.123 ns) = 1.816 ns; Loc. = LC_X12_Y8_N2; Fanout = 2; COMB Node = 'PWM:inst3\|Add2~127'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.123 ns" { PWM:inst3|Add2~129 PWM:inst3|Add2~127 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1111 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 1.939 ns PWM:inst3\|Add2~125 4 COMB LC_X12_Y8_N3 2 " "Info: 4: + IC(0.000 ns) + CELL(0.123 ns) = 1.939 ns; Loc. = LC_X12_Y8_N3; Fanout = 2; COMB Node = 'PWM:inst3\|Add2~125'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.123 ns" { PWM:inst3|Add2~127 PWM:inst3|Add2~125 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1111 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.815 ns) 2.754 ns PWM:inst3\|Add2~122 5 COMB LC_X12_Y8_N4 1 " "Info: 5: + IC(0.000 ns) + CELL(0.815 ns) = 2.754 ns; Loc. = LC_X12_Y8_N4; Fanout = 1; COMB Node = 'PWM:inst3\|Add2~122'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.815 ns" { PWM:inst3|Add2~125 PWM:inst3|Add2~122 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1111 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.821 ns) + CELL(0.954 ns) 5.529 ns PWM:inst3\|LessThan0~461 6 COMB LC_X13_Y8_N4 1 " "Info: 6: + IC(1.821 ns) + CELL(0.954 ns) = 5.529 ns; Loc. = LC_X13_Y8_N4; Fanout = 1; COMB Node = 'PWM:inst3\|LessThan0~461'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.775 ns" { PWM:inst3|Add2~122 PWM:inst3|LessThan0~461 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1695 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.975 ns) 6.504 ns PWM:inst3\|LessThan0~443 7 COMB LC_X13_Y8_N7 1 " "Info: 7: + IC(0.000 ns) + CELL(0.975 ns) = 6.504 ns; Loc. = LC_X13_Y8_N7; Fanout = 1; COMB Node = 'PWM:inst3\|LessThan0~443'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.975 ns" { PWM:inst3|LessThan0~461 PWM:inst3|LessThan0~443 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1695 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 7.009 ns PWM:inst3\|LessThan0~448 8 COMB LC_X13_Y8_N8 1 " "Info: 8: + IC(0.305 ns) + CELL(0.200 ns) = 7.009 ns; Loc. = LC_X13_Y8_N8; Fanout = 1; COMB Node = 'PWM:inst3\|LessThan0~448'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.505 ns" { PWM:inst3|LessThan0~443 PWM:inst3|LessThan0~448 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1695 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.023 ns) + CELL(2.322 ns) 12.354 ns to_servo 9 PIN PIN_140 0 " "Info: 9: + IC(3.023 ns) + CELL(2.322 ns) = 12.354 ns; Loc. = PIN_140; Fanout = 0; PIN Node = 'to_servo'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.345 ns" { PWM:inst3|LessThan0~448 to_servo } "NODE_NAME" } } { "test.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/test.bdf" { { 304 552 728 320 "to_servo" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.490 ns ( 52.53 % ) " "Info: Total cell delay = 6.490 ns ( 52.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.864 ns ( 47.47 % ) " "Info: Total interconnect delay = 5.864 ns ( 47.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.354 ns" { SEL:inst2|Motor_Width_Ctr[1] PWM:inst3|Add2~129 PWM:inst3|Add2~127 PWM:inst3|Add2~125 PWM:inst3|Add2~122 PWM:inst3|LessThan0~461 PWM:inst3|LessThan0~443 PWM:inst3|LessThan0~448 to_servo } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "12.354 ns" { SEL:inst2|Motor_Width_Ctr[1] PWM:inst3|Add2~129 PWM:inst3|Add2~127 PWM:inst3|Add2~125 PWM:inst3|Add2~122 PWM:inst3|LessThan0~461 PWM:inst3|LessThan0~443 PWM:inst3|LessThan0~448 to_servo } { 0.000ns 0.715ns 0.000ns 0.000ns 0.000ns 1.821ns 0.000ns 0.305ns 3.023ns } { 0.000ns 0.978ns 0.123ns 0.123ns 0.815ns 0.954ns 0.975ns 0.200ns 2.322ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "15.603 ns" { clk RxUnit:inst|DOut[7] SEL:inst2|comb~0 SEL:inst2|Motor_Width_Ctr[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "15.603 ns" { clk clk~combout RxUnit:inst|DOut[7] SEL:inst2|comb~0 SEL:inst2|Motor_Width_Ctr[1] } { 0.000ns 0.000ns 5.287ns 2.026ns 4.613ns } { 0.000ns 1.132ns 1.294ns 0.740ns 0.511ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.354 ns" { SEL:inst2|Motor_Width_Ctr[1] PWM:inst3|Add2~129 PWM:inst3|Add2~127 PWM:inst3|Add2~125 PWM:inst3|Add2~122 PWM:inst3|LessThan0~461 PWM:inst3|LessThan0~443 PWM:inst3|LessThan0~448 to_servo } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "12.354 ns" { SEL:inst2|Motor_Width_Ctr[1] PWM:inst3|Add2~129 PWM:inst3|Add2~127 PWM:inst3|Add2~125 PWM:inst3|Add2~122 PWM:inst3|LessThan0~461 PWM:inst3|LessThan0~443 PWM:inst3|LessThan0~448 to_servo } { 0.000ns 0.715ns 0.000ns 0.000ns 0.000ns 1.821ns 0.000ns 0.305ns 3.023ns } { 0.000ns 0.978ns 0.123ns 0.123ns 0.815ns 0.954ns 0.975ns 0.200ns 2.322ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "RxUnit:inst\|ShtReg\[4\] remote clk 2.674 ns register " "Info: th for register \"RxUnit:inst\|ShtReg\[4\]\" (data pin = \"remote\", clock pin = \"clk\") is 2.674 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.337 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 7.337 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 46 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 46; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "test.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/test.bdf" { { 24 -24 144 40 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.287 ns) + CELL(0.918 ns) 7.337 ns RxUnit:inst\|ShtReg\[4\] 2 REG LC_X9_Y7_N0 2 " "Info: 2: + IC(5.287 ns) + CELL(0.918 ns) = 7.337 ns; Loc. = LC_X9_Y7_N0; Fanout = 2; REG Node = 'RxUnit:inst\|ShtReg\[4\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.205 ns" { clk RxUnit:inst|ShtReg[4] } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/RxUnit.vhd" 80 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns ( 27.94 % ) " "Info: Total cell delay = 2.050 ns ( 27.94 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.287 ns ( 72.06 % ) " "Info: Total interconnect delay = 5.287 ns ( 72.06 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.337 ns" { clk RxUnit:inst|ShtReg[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.337 ns" { clk clk~combout RxUnit:inst|ShtReg[4] } { 0.000ns 0.000ns 5.287ns } { 0.000ns 1.132ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "RxUnit.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/RxUnit.vhd" 80 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.884 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.884 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns remote 1 PIN PIN_138 26 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_138; Fanout = 26; PIN Node = 'remote'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { remote } "NODE_NAME" } } { "test.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/test.bdf" { { 152 -288 -120 168 "remote" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.948 ns) + CELL(0.804 ns) 4.884 ns RxUnit:inst\|ShtReg\[4\] 2 REG LC_X9_Y7_N0 2 " "Info: 2: + IC(2.948 ns) + CELL(0.804 ns) = 4.884 ns; Loc. = LC_X9_Y7_N0; Fanout = 2; REG Node = 'RxUnit:inst\|ShtReg\[4\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.752 ns" { remote RxUnit:inst|ShtReg[4] } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/RxUnit.vhd" 80 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.936 ns ( 39.64 % ) " "Info: Total cell delay = 1.936 ns ( 39.64 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.948 ns ( 60.36 % ) " "Info: Total interconnect delay = 2.948 ns ( 60.36 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.884 ns" { remote RxUnit:inst|ShtReg[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.884 ns" { remote remote~combout RxUnit:inst|ShtReg[4] } { 0.000ns 0.000ns 2.948ns } { 0.000ns 1.132ns 0.804ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.337 ns" { clk RxUnit:inst|ShtReg[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.337 ns" { clk clk~combout RxUnit:inst|ShtReg[4] } { 0.000ns 0.000ns 5.287ns } { 0.000ns 1.132ns 0.918ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.884 ns" { remote RxUnit:inst|ShtReg[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.884 ns" { remote remote~combout RxUnit:inst|ShtReg[4] } { 0.000ns 0.000ns 2.948ns } { 0.000ns 1.132ns 0.804ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 18 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 18 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 09 10:48:44 2007 " "Info: Processing ended: Tue Oct 09 10:48:44 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}