test.tan.qmsg

两路电机CPLD控制,串口通信

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register RxUnit:inst\|BitCnt\[1\] register RxUnit:inst\|DOut\[6\] 123.66 MHz 8.087 ns Internal " "Info: Clock \"clk\" has Internal fmax of 123.66 MHz between source register \"RxUnit:inst\|BitCnt\[1\]\" and destination register \"RxUnit:inst\|DOut\[6\]\" (period= 8.087 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.378 ns + Longest register register " "Info: + Longest register to register delay is 7.378 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns RxUnit:inst\|BitCnt\[1\] 1 REG LC_X8_Y7_N6 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y7_N6; Fanout = 6; REG Node = 'RxUnit:inst\|BitCnt\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { RxUnit:inst|BitCnt[1] } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/RxUnit.vhd" 80 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.384 ns) + CELL(0.511 ns) 1.895 ns RxUnit:inst\|ShtReg\[4\]~657 2 COMB LC_X7_Y7_N6 4 " "Info: 2: + IC(1.384 ns) + CELL(0.511 ns) = 1.895 ns; Loc. = LC_X7_Y7_N6; Fanout = 4; COMB Node = 'RxUnit:inst\|ShtReg\[4\]~657'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.895 ns" { RxUnit:inst|BitCnt[1] RxUnit:inst|ShtReg[4]~657 } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/RxUnit.vhd" 80 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.663 ns) + CELL(0.740 ns) 4.298 ns RxUnit:inst\|DOut\[5\]~546 3 COMB LC_X9_Y7_N8 8 " "Info: 3: + IC(1.663 ns) + CELL(0.740 ns) = 4.298 ns; Loc. = LC_X9_Y7_N8; Fanout = 8; COMB Node = 'RxUnit:inst\|DOut\[5\]~546'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.403 ns" { RxUnit:inst|ShtReg[4]~657 RxUnit:inst|DOut[5]~546 } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/RxUnit.vhd" 80 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.837 ns) + CELL(1.243 ns) 7.378 ns RxUnit:inst\|DOut\[6\] 4 REG LC_X8_Y8_N4 2 " "Info: 4: + IC(1.837 ns) + CELL(1.243 ns) = 7.378 ns; Loc. = LC_X8_Y8_N4; Fanout = 2; REG Node = 'RxUnit:inst\|DOut\[6\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.080 ns" { RxUnit:inst|DOut[5]~546 RxUnit:inst|DOut[6] } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/RxUnit.vhd" 80 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.494 ns ( 33.80 % ) " "Info: Total cell delay = 2.494 ns ( 33.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.884 ns ( 66.20 % ) " "Info: Total interconnect delay = 4.884 ns ( 66.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.378 ns" { RxUnit:inst|BitCnt[1] RxUnit:inst|ShtReg[4]~657 RxUnit:inst|DOut[5]~546 RxUnit:inst|DOut[6] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.378 ns" { RxUnit:inst|BitCnt[1] RxUnit:inst|ShtReg[4]~657 RxUnit:inst|DOut[5]~546 RxUnit:inst|DOut[6] } { 0.000ns 1.384ns 1.663ns 1.837ns } { 0.000ns 0.511ns 0.740ns 1.243ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.337 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 7.337 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 46 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 46; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "test.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/test.bdf" { { 24 -24 144 40 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.287 ns) + CELL(0.918 ns) 7.337 ns RxUnit:inst\|DOut\[6\] 2 REG LC_X8_Y8_N4 2 " "Info: 2: + IC(5.287 ns) + CELL(0.918 ns) = 7.337 ns; Loc. = LC_X8_Y8_N4; Fanout = 2; REG Node = 'RxUnit:inst\|DOut\[6\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.205 ns" { clk RxUnit:inst|DOut[6] } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/RxUnit.vhd" 80 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns ( 27.94 % ) " "Info: Total cell delay = 2.050 ns ( 27.94 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.287 ns ( 72.06 % ) " "Info: Total interconnect delay = 5.287 ns ( 72.06 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.337 ns" { clk RxUnit:inst|DOut[6] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.337 ns" { clk clk~combout RxUnit:inst|DOut[6] } { 0.000ns 0.000ns 5.287ns } { 0.000ns 1.132ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.337 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 7.337 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 46 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 46; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "test.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/test.bdf" { { 24 -24 144 40 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.287 ns) + CELL(0.918 ns) 7.337 ns RxUnit:inst\|BitCnt\[1\] 2 REG LC_X8_Y7_N6 6 " "Info: 2: + IC(5.287 ns) + CELL(0.918 ns) = 7.337 ns; Loc. = LC_X8_Y7_N6; Fanout = 6; REG Node = 'RxUnit:inst\|BitCnt\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.205 ns" { clk RxUnit:inst|BitCnt[1] } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/RxUnit.vhd" 80 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns ( 27.94 % ) " "Info: Total cell delay = 2.050 ns ( 27.94 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.287 ns ( 72.06 % ) " "Info: Total interconnect delay = 5.287 ns ( 72.06 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.337 ns" { clk RxUnit:inst|BitCnt[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.337 ns" { clk clk~combout RxUnit:inst|BitCnt[1] } { 0.000ns 0.000ns 5.287ns } { 0.000ns 1.132ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.337 ns" { clk RxUnit:inst|DOut[6] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.337 ns" { clk clk~combout RxUnit:inst|DOut[6] } { 0.000ns 0.000ns 5.287ns } { 0.000ns 1.132ns 0.918ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.337 ns" { clk RxUnit:inst|BitCnt[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.337 ns" { clk clk~combout RxUnit:inst|BitCnt[1] } { 0.000ns 0.000ns 5.287ns } { 0.000ns 1.132ns 0.918ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "RxUnit.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/RxUnit.vhd" 80 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "RxUnit.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/RxUnit.vhd" 80 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.378 ns" { RxUnit:inst|BitCnt[1] RxUnit:inst|ShtReg[4]~657 RxUnit:inst|DOut[5]~546 RxUnit:inst|DOut[6] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.378 ns" { RxUnit:inst|BitCnt[1] RxUnit:inst|ShtReg[4]~657 RxUnit:inst|DOut[5]~546 RxUnit:inst|DOut[6] } { 0.000ns 1.384ns 1.663ns 1.837ns } { 0.000ns 0.511ns 0.740ns 1.243ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.337 ns" { clk RxUnit:inst|DOut[6] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.337 ns" { clk clk~combout RxUnit:inst|DOut[6] } { 0.000ns 0.000ns 5.287ns } { 0.000ns 1.132ns 0.918ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.337 ns" { clk RxUnit:inst|BitCnt[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.337 ns" { clk clk~combout RxUnit:inst|BitCnt[1] } { 0.000ns 0.000ns 5.287ns } { 0.000ns 1.132ns 0.918ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 14 " "Warning: Circuit may not operate. Detected 14 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "RxUnit:inst\|DOut\[5\] SEL:inst2\|Servo_Width_Ctr\[5\] clk 5.976 ns " "Info: Found hold time violation between source  pin or register \"RxUnit:inst\|DOut\[5\]\" and destination pin or register \"SEL:inst2\|Servo_Width_Ctr\[5\]\" for clock \"clk\" (Hold time is 5.976 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "7.989 ns + Largest " "Info: + Largest clock skew is 7.989 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 15.326 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 15.326 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 46 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 46; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "test.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/test.bdf" { { 24 -24 144 40 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.287 ns) + CELL(1.294 ns) 7.713 ns RxUnit:inst\|DOut\[7\] 2 REG LC_X10_Y7_N7 2 " "Info: 2: + IC(5.287 ns) + CELL(1.294 ns) = 7.713 ns; Loc. = LC_X10_Y7_N7; Fanout = 2; REG Node = 'RxUnit:inst\|DOut\[7\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.581 ns" { clk RxUnit:inst|DOut[7] } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/RxUnit.vhd" 80 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.029 ns) + CELL(0.200 ns) 9.942 ns SEL:inst2\|comb~1 3 COMB LC_X10_Y4_N3 7 " "Info: 3: + IC(2.029 ns) + CELL(0.200 ns) = 9.942 ns; Loc. = LC_X10_Y4_N3; Fanout = 7; COMB Node = 'SEL:inst2\|comb~1'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.229 ns" { RxUnit:inst|DOut[7] SEL:inst2|comb~1 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.184 ns) + CELL(0.200 ns) 15.326 ns SEL:inst2\|Servo_Width_Ctr\[5\] 4 REG LC_X8_Y8_N6 3 " "Info: 4: + IC(5.184 ns) + CELL(0.200 ns) = 15.326 ns; Loc. = LC_X8_Y8_N6; Fanout = 3; REG Node = 'SEL:inst2\|Servo_Width_Ctr\[5\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.384 ns" { SEL:inst2|comb~1 SEL:inst2|Servo_Width_Ctr[5] } "NODE_NAME" } } { "SEL.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/SEL.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.826 ns ( 18.44 % ) " "Info: Total cell delay = 2.826 ns ( 18.44 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "12.500 ns ( 81.56 % ) " "Info: Total interconnect delay = 12.500 ns ( 81.56 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "15.326 ns" { clk RxUnit:inst|DOut[7] SEL:inst2|comb~1 SEL:inst2|Servo_Width_Ctr[5] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "15.326 ns" { clk clk~combout RxUnit:inst|DOut[7] SEL:inst2|comb~1 SEL:inst2|Servo_Width_Ctr[5] } { 0.000ns 0.000ns 5.287ns 2.029ns 5.184ns } { 0.000ns 1.132ns 1.294ns 0.200ns 0.200ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.337 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 7.337 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 46 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 46; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "test.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/test.bdf" { { 24 -24 144 40 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.287 ns) + CELL(0.918 ns) 7.337 ns RxUnit:inst\|DOut\[5\] 2 REG LC_X8_Y8_N1 2 " "Info: 2: + IC(5.287 ns) + CELL(0.918 ns) = 7.337 ns; Loc. = LC_X8_Y8_N1; Fanout = 2; REG Node = 'RxUnit:inst\|DOut\[5\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.205 ns" { clk RxUnit:inst|DOut[5] } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/RxUnit.vhd" 80 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns ( 27.94 % ) " "Info: Total cell delay = 2.050 ns ( 27.94 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.287 ns ( 72.06 % ) " "Info: Total interconnect delay = 5.287 ns ( 72.06 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.337 ns" { clk RxUnit:inst|DOut[5] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.337 ns" { clk clk~combout RxUnit:inst|DOut[5] } { 0.000ns 0.000ns 5.287ns } { 0.000ns 1.132ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "15.326 ns" { clk RxUnit:inst|DOut[7] SEL:inst2|comb~1 SEL:inst2|Servo_Width_Ctr[5] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "15.326 ns" { clk clk~combout RxUnit:inst|DOut[7] SEL:inst2|comb~1 SEL:inst2|Servo_Width_Ctr[5] } { 0.000ns 0.000ns 5.287ns 2.029ns 5.184ns } { 0.000ns 1.132ns 1.294ns 0.200ns 0.200ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.337 ns" { clk RxUnit:inst|DOut[5] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.337 ns" { clk clk~combout RxUnit:inst|DOut[5] } { 0.000ns 0.000ns 5.287ns } { 0.000ns 1.132ns 0.918ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns - " "Info: - Micro clock to output delay of source is 0.376 ns" {  } { { "RxUnit.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/RxUnit.vhd" 80 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.637 ns - Shortest register register " "Info: - Shortest register to register delay is 1.637 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns RxUnit:inst\|DOut\[5\] 1 REG LC_X8_Y8_N1 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y8_N1; Fanout = 2; REG Node = 'RxUnit:inst\|DOut\[5\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { RxUnit:inst|DOut[5] } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/RxUnit.vhd" 80 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.897 ns) + CELL(0.740 ns) 1.637 ns SEL:inst2\|Servo_Width_Ctr\[5\] 2 REG LC_X8_Y8_N6 3 " "Info: 2: + IC(0.897 ns) + CELL(0.740 ns) = 1.637 ns; Loc. = LC_X8_Y8_N6; Fanout = 3; REG Node = 'SEL:inst2\|Servo_Width_Ctr\[5\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.637 ns" { RxUnit:inst|DOut[5] SEL:inst2|Servo_Width_Ctr[5] } "NODE_NAME" } } { "SEL.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/SEL.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.740 ns ( 45.20 % ) " "Info: Total cell delay = 0.740 ns ( 45.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.897 ns ( 54.80 % ) " "Info: Total interconnect delay = 0.897 ns ( 54.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.637 ns" { RxUnit:inst|DOut[5] SEL:inst2|Servo_Width_Ctr[5] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "1.637 ns" { RxUnit:inst|DOut[5] SEL:inst2|Servo_Width_Ctr[5] } { 0.000ns 0.897ns } { 0.000ns 0.740ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "SEL.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/SEL.vhd" 27 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "RxUnit.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/RxUnit.vhd" 80 -1 0 } } { "SEL.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/SEL.vhd" 27 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "15.326 ns" { clk RxUnit:inst|DOut[7] SEL:inst2|comb~1 SEL:inst2|Servo_Width_Ctr[5] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "15.326 ns" { clk clk~combout RxUnit:inst|DOut[7] SEL:inst2|comb~1 SEL:inst2|Servo_Width_Ctr[5] } { 0.000ns 0.000ns 5.287ns 2.029ns 5.184ns } { 0.000ns 1.132ns 1.294ns 0.200ns 0.200ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.337 ns" { clk RxUnit:inst|DOut[5] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.337 ns" { clk clk~combout RxUnit:inst|DOut[5] } { 0.000ns 0.000ns 5.287ns } { 0.000ns 1.132ns 0.918ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.637 ns" { RxUnit:inst|DOut[5] SEL:inst2|Servo_Width_Ctr[5] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "1.637 ns" { RxUnit:inst|DOut[5] SEL:inst2|Servo_Width_Ctr[5] } { 0.000ns 0.897ns } { 0.000ns 0.740ns } } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "RxUnit:inst\|DOut\[6\] rst clk 2.280 ns register " "Info: tsu for register \"RxUnit:inst\|DOut\[6\]\" (data pin = \"rst\", clock pin = \"clk\") is 2.280 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.284 ns + Longest pin register " "Info: + Longest pin to register delay is 9.284 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns rst 1 PIN PIN_110 26 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_110; Fanout = 26; PIN Node = 'rst'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { rst } "NODE_NAME" } } { "test.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/test.bdf" { { 88 -96 72 104 "rst" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.548 ns) + CELL(0.200 ns) 4.880 ns inst7~62 2 COMB LC_X9_Y7_N7 29 " "Info: 2: + IC(3.548 ns) + CELL(0.200 ns) = 4.880 ns; Loc. = LC_X9_Y7_N7; Fanout = 29; COMB Node = 'inst7~62'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.748 ns" { rst inst7~62 } "NODE_NAME" } } { "test.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/test.bdf" { { 112 88 152 160 "inst7" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.813 ns) + CELL(0.511 ns) 6.204 ns RxUnit:inst\|DOut\[5\]~546 3 COMB LC_X9_Y7_N8 8 " "Info: 3: + IC(0.813 ns) + CELL(0.511 ns) = 6.204 ns; Loc. = LC_X9_Y7_N8; Fanout = 8; COMB Node = 'RxUnit:inst\|DOut\[5\]~546'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.324 ns" { inst7~62 RxUnit:inst|DOut[5]~546 } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/RxUnit.vhd" 80 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.837 ns) + CELL(1.243 ns) 9.284 ns RxUnit:inst\|DOut\[6\] 4 REG LC_X8_Y8_N4 2 " "Info: 4: + IC(1.837 ns) + CELL(1.243 ns) = 9.284 ns; Loc. = LC_X8_Y8_N4; Fanout = 2; REG Node = 'RxUnit:inst\|DOut\[6\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.080 ns" { RxUnit:inst|DOut[5]~546 RxUnit:inst|DOut[6] } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/RxUnit.vhd" 80 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.086 ns ( 33.24 % ) " "Info: Total cell delay = 3.086 ns ( 33.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.198 ns ( 66.76 % ) " "Info: Total interconnect delay = 6.198 ns ( 66.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.284 ns" { rst inst7~62 RxUnit:inst|DOut[5]~546 RxUnit:inst|DOut[6] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "9.284 ns" { rst rst~combout inst7~62 RxUnit:inst|DOut[5]~546 RxUnit:inst|DOut[6] } { 0.000ns 0.000ns 3.548ns 0.813ns 1.837ns } { 0.000ns 1.132ns 0.200ns 0.511ns 1.243ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "RxUnit.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/RxUnit.vhd" 80 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.337 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 7.337 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 46 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 46; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "test.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/test.bdf" { { 24 -24 144 40 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.287 ns) + CELL(0.918 ns) 7.337 ns RxUnit:inst\|DOut\[6\] 2 REG LC_X8_Y8_N4 2 " "Info: 2: + IC(5.287 ns) + CELL(0.918 ns) = 7.337 ns; Loc. = LC_X8_Y8_N4; Fanout = 2; REG Node = 'RxUnit:inst\|DOut\[6\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.205 ns" { clk RxUnit:inst|DOut[6] } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/RxUnit.vhd" 80 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns ( 27.94 % ) " "Info: Total cell delay = 2.050 ns ( 27.94 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.287 ns ( 72.06 % ) " "Info: Total interconnect delay = 5.287 ns ( 72.06 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.337 ns" { clk RxUnit:inst|DOut[6] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.337 ns" { clk clk~combout RxUnit:inst|DOut[6] } { 0.000ns 0.000ns 5.287ns } { 0.000ns 1.132ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.284 ns" { rst inst7~62 RxUnit:inst|DOut[5]~546 RxUnit:inst|DOut[6] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "9.284 ns" { rst rst~combout inst7~62 RxUnit:inst|DOut[5]~546 RxUnit:inst|DOut[6] } { 0.000ns 0.000ns 3.548ns 0.813ns 1.837ns } { 0.000ns 1.132ns 0.200ns 0.511ns 1.243ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.337 ns" { clk RxUnit:inst|DOut[6] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.337 ns" { clk clk~combout RxUnit:inst|DOut[6] } { 0.000ns 0.000ns 5.287ns } { 0.000ns 1.132ns 0.918ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}