test.tan.qmsg

两路电机CPLD控制,串口通信

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "SEL:inst2\|Servo_Width_Ctr\[6\] " "Warning: Node \"SEL:inst2\|Servo_Width_Ctr\[6\]\" is a latch" {  } { { "SEL.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/SEL.vhd" 27 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "SEL:inst2\|Servo_Width_Ctr\[4\] " "Warning: Node \"SEL:inst2\|Servo_Width_Ctr\[4\]\" is a latch" {  } { { "SEL.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/SEL.vhd" 27 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "SEL:inst2\|Motor_Width_Ctr\[6\] " "Warning: Node \"SEL:inst2\|Motor_Width_Ctr\[6\]\" is a latch" {  } { { "SEL.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/SEL.vhd" 27 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "SEL:inst2\|Motor_Width_Ctr\[4\] " "Warning: Node \"SEL:inst2\|Motor_Width_Ctr\[4\]\" is a latch" {  } { { "SEL.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/SEL.vhd" 27 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "SEL:inst2\|Servo_Width_Ctr\[5\] " "Warning: Node \"SEL:inst2\|Servo_Width_Ctr\[5\]\" is a latch" {  } { { "SEL.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/SEL.vhd" 27 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "SEL:inst2\|Motor_Width_Ctr\[5\] " "Warning: Node \"SEL:inst2\|Motor_Width_Ctr\[5\]\" is a latch" {  } { { "SEL.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/SEL.vhd" 27 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "SEL:inst2\|Servo_Width_Ctr\[3\] " "Warning: Node \"SEL:inst2\|Servo_Width_Ctr\[3\]\" is a latch" {  } { { "SEL.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/SEL.vhd" 27 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "SEL:inst2\|Servo_Width_Ctr\[2\] " "Warning: Node \"SEL:inst2\|Servo_Width_Ctr\[2\]\" is a latch" {  } { { "SEL.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/SEL.vhd" 27 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "SEL:inst2\|Motor_Width_Ctr\[3\] " "Warning: Node \"SEL:inst2\|Motor_Width_Ctr\[3\]\" is a latch" {  } { { "SEL.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/SEL.vhd" 27 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "SEL:inst2\|Motor_Width_Ctr\[2\] " "Warning: Node \"SEL:inst2\|Motor_Width_Ctr\[2\]\" is a latch" {  } { { "SEL.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/SEL.vhd" 27 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "SEL:inst2\|Servo_Width_Ctr\[1\] " "Warning: Node \"SEL:inst2\|Servo_Width_Ctr\[1\]\" is a latch" {  } { { "SEL.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/SEL.vhd" 27 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "SEL:inst2\|Motor_Width_Ctr\[1\] " "Warning: Node \"SEL:inst2\|Motor_Width_Ctr\[1\]\" is a latch" {  } { { "SEL.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/SEL.vhd" 27 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "SEL:inst2\|Servo_Width_Ctr\[0\] " "Warning: Node \"SEL:inst2\|Servo_Width_Ctr\[0\]\" is a latch" {  } { { "SEL.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/SEL.vhd" 27 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "SEL:inst2\|Motor_Width_Ctr\[0\] " "Warning: Node \"SEL:inst2\|Motor_Width_Ctr\[0\]\" is a latch" {  } { { "SEL.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/SEL.vhd" 27 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "test.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/test.bdf" { { 24 -24 144 40 "clk" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "5 " "Warning: Found 5 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "SEL:inst2\|comb~0 " "Info: Detected gated clock \"SEL:inst2\|comb~0\" as buffer" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "SEL:inst2\|comb~0" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "RxUnit:inst\|DOut\[7\] " "Info: Detected ripple clock \"RxUnit:inst\|DOut\[7\]\" as buffer" {  } { { "RxUnit.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/RxUnit.vhd" 80 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "RxUnit:inst\|DOut\[7\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "RxUnit:inst\|tmpDRdy " "Info: Detected ripple clock \"RxUnit:inst\|tmpDRdy\" as buffer" {  } { { "RxUnit.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/RxUnit.vhd" 80 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "RxUnit:inst\|tmpDRdy" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "SEL:inst2\|comb~1 " "Info: Detected gated clock \"SEL:inst2\|comb~1\" as buffer" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "SEL:inst2\|comb~1" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "PWM:inst3\|clk_servo " "Info: Detected ripple clock \"PWM:inst3\|clk_servo\" as buffer" {  } { { "PWM.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/test/遥控vhdl/PWM.vhd" 30 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "PWM:inst3\|clk_servo" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}