test.map.summary

两路电机CPLD控制,串口通信

Analysis & Synthesis Status : Successful - Tue Oct 09 10:48:37 2007
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : test
Top-level Entity Name : test
Family : MAX II
Total logic elements : 165
Total pins : 6
Total virtual pins : 0
UFM blocks : 0