smartsopc_standard_1c12.tan.rpt

华清远见 高级的培训 实验代码

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+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                    ;
+---------------------------------------------------------+-----------+----------------------------------+------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------+------------------------------------------+--------------+
; Type                                                    ; Slack     ; Required Time                    ; Actual Time                                    ; From                                                                                                                                  ; To                                                                                                                                                                                  ; From Clock                               ; To Clock                                 ; Failed Paths ;
+---------------------------------------------------------+-----------+----------------------------------+------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------+------------------------------------------+--------------+
; Worst-case tsu                                          ; N/A       ; None                             ; 10.222 ns                                      ; IR_RX                                                                                                                                 ; niso2_1c12:inst|infrared_uart:the_infrared_uart|infrared_uart_rx:the_infrared_uart_rx|d1_source_rxd                                                                                 ;                                          ; SYS_CLK2                                 ; 0            ;
; Worst-case tco                                          ; N/A       ; None                             ; 12.007 ns                                      ; lcd_delay:inst2|delay_block:inst17|delay_counter:inst|lpm_counter:lpm_counter_component|cntr_ud8:auto_generated|safe_q[1]             ; A[0]                                                                                                                                                                                ; SYS_CLK2                                 ;                                          ; 0            ;
; Worst-case tpd                                          ; N/A       ; None                             ; 2.124 ns                                       ; altera_internal_jtag~TDO                                                                                                              ; altera_reserved_tdo                                                                                                                                                                 ;                                          ;                                          ; 0            ;
; Worst-case th                                           ; N/A       ; None                             ; 4.571 ns                                       ; altera_internal_jtag                                                                                                                  ; niso2_1c12:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[37] ;                                          ; altera_internal_jtag~TCKUTAP             ; 0            ;
; Clock Setup: 'pll:inst21|altpll:altpll_component|_clk0' ; 1.683 ns  ; 48.00 MHz ( period = 20.833 ns ) ; 52.22 MHz ( period = 19.150 ns )               ; niso2_1c12:inst|cpu:the_cpu|W_alu_result[15]                                                                                          ; niso2_1c12:inst|ext_bus_avalon_slave_arbitrator:the_ext_bus_avalon_slave|ext_bus_address[9]                                                                                         ; pll:inst21|altpll:altpll_component|_clk0 ; pll:inst21|altpll:altpll_component|_clk0 ; 0            ;
; Clock Setup: 'SYS_CLK2'                                 ; 15.757 ns ; 48.00 MHz ( period = 20.833 ns ) ; 197.01 MHz ( period = 5.076 ns )               ; delay_reset_block:inst20|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_df8:auto_generated|safe_q[2]                       ; delay_reset_block:inst20|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_df8:auto_generated|safe_q[3]                                                                     ; SYS_CLK2                                 ; SYS_CLK2                                 ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP'             ; N/A       ; None                             ; 88.83 MHz ( period = 11.257 ns )               ; sld_hub:sld_hub_inst|jtag_debug_mode_usr1                                                                                             ; niso2_1c12:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[16] ; altera_internal_jtag~TCKUTAP             ; altera_internal_jtag~TCKUTAP             ; 0            ;
; Clock Setup: 'FREQ_INPUT'                               ; N/A       ; None                             ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; niso2_1c12:inst|cymometer:the_cymometer|cymometer_avalon_interface:the_cymometer_avalon_interface|cymometer_task_logic:U1|pre_freq[2] ; niso2_1c12:inst|cymometer:the_cymometer|cymometer_avalon_interface:the_cymometer_avalon_interface|cymometer_task_logic:U1|pre_freq[31]                                              ; FREQ_INPUT                               ; FREQ_INPUT                               ; 0            ;
; Clock Hold: 'pll:inst21|altpll:altpll_component|_clk0'  ; 0.822 ns  ; 48.00 MHz ( period = 20.833 ns ) ; N/A                                            ; niso2_1c12:inst|jtag_uart:the_jtag_uart|av_waitrequest                                                                                ; niso2_1c12:inst|jtag_uart:the_jtag_uart|av_waitrequest                                                                                                                              ; pll:inst21|altpll:altpll_component|_clk0 ; pll:inst21|altpll:altpll_component|_clk0 ; 0            ;
; Clock Hold: 'SYS_CLK2'                                  ; 1.312 ns  ; 48.00 MHz ( period = 20.833 ns ) ; N/A                                            ; delay_reset_block:inst20|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_df8:auto_generated|safe_q[0]                       ; delay_reset_block:inst20|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_df8:auto_generated|safe_q[0]                                                                     ; SYS_CLK2                                 ; SYS_CLK2                                 ; 0            ;
; Total number of failed paths                            ;           ;                                  ;                                                ;                                                                                                                                       ;                                                                                                                                                                                     ;                                          ;                                          ; 0            ;
+---------------------------------------------------------+-----------+----------------------------------+------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------+------------------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C6Q240C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;