seven_segdisp_register_file.v

华清远见 高级的培训 实验代码

/****************************************Copyright (c)**************************************************
**                               Guangzhou ZHIYUAN ELECTRONIC CO.,LTD.
**                                      Research centre
**                         http://www.zyinside.com, http://www.zlgmcu.com
**
**---------------------------------------File Info-----------------------------------------------------
** File name:			seven_segdisp_register_file.v
** Last modified Date:	2005-12-13
** Last Version:		1.0
** Descriptions:		the register file of the Seven segments led driver logic
**------------------------------------------------------------------------------------------------------
** Created by:			LiuYingbin
** Created date:		2005-12-13
** Version:				1.0
** Descriptions:		The original version
**
**------------------------------------------------------------------------------------------------------
** Modified by:			
** Modified date:		
** Version:				
** Descriptions:		
**
**------------------------------------------------------------------------------------------------------
********************************************************************************************************/
module seven_segdisp_register_file(	
	//Avalon Signals
	clock,
	reset_n, 
	chip_select,
	address,
	write,
	write_data,
	read,
	read_data,

	//seven_segdisp Output Signals
	seven_segdisp_enable,   //seven_segdisp driver logic enable signal
	seven_segdisp_addr,     //signal to enable a seven_segdisp
	seg_data        		//signals to tell outside what to display
);

//Parameters
		input 			clock;			    //System Clock
		input 			reset_n;			//System Reset
		input 			chip_select;		//Avalon Chip select signal
		input [3:0] 	address;	     	//Avalon Address bus 
		input 			write;				//Avalon Write signal
		input [31:0] 	write_data;			//Avalon Write data bus
		input 			read;			    //Avalon read signal
		output[31:0] 	read_data;	  		//Avalon read data bus

		output[7:0] 	seg_data; 	        //signals to tell outside what to display
		output[2:0] 	seven_segdisp_addr; //signal to enable a seven_segdisp
		output        	seven_segdisp_enable;//seven_segdisp enable drive signals

//Signal Declarations	
reg [7:0]   data_r[7:0];        //data register
reg        	enable_r;	 		//Enable Bit 0: disable; 1: enable	
reg         inner_clk;
reg [7:0]  	read_data_r;        //Read_data bus
reg [17:0]  seven_segdisp_cnt;  //seven_segdisp counter
reg [2:0]   seven_segdisp_addr_r;
reg [2:0]   data_addr;
reg [7:0]   seg_data_r;
wire		write_act,read_act;


//determine if a vaild transaction was initiated 
assign write_act = chip_select & write;		
assign read_act  = chip_select & read;

				
//write
always @(posedge clock or negedge reset_n)
begin
	if (~reset_n)
	begin
		//initializtion
        data_r[0] <= 8'b11111111;
        data_r[1] <= 8'b11111111;
		data_r[2] <= 8'b11111111;
		data_r[3] <= 8'b11111111;
        data_r[4] <= 8'b11111111;
        data_r[5] <= 8'b11111111;
		data_r[6] <= 8'b11111111;
		data_r[7] <= 8'b11111111;
		enable_r <= 1'b0;
	end
	else if (write_act)
	begin
		case (address)
			4'h0:
			begin
				data_r[0] <= write_data[7:0];
			end
			4'h1:
			begin
				data_r[1] <= write_data[7:0];
			end
			4'h2:
			begin
				data_r[2] <= write_data[7:0];
			end
			4'h3:
			begin
				data_r[3] <= write_data[7:0];
			end
			4'h4:
			begin
				data_r[4] <= write_data[7:0];
			end
			4'h5:
			begin
				data_r[5] <= write_data[7:0];
			end
			4'h6:
			begin
				data_r[6] <= write_data[7:0];
			end
			4'h7:
			begin
				data_r[7] <= write_data[7:0];
			end
			4'h8:
			begin
				enable_r <= write_data[0];
			end
			
			default:
			begin
			end
		endcase
	end
end

always @(posedge clock)
begin
	if (read_act)
	begin
		case (address)
			4'h0:
			begin
				read_data_r <= data_r[0];
			end
				
			4'h1:
			begin
				read_data_r <= data_r[1];
			end
				
			4'h2:
			begin
				read_data_r <= data_r[2];
			end
			
			4'h3:
			begin
				read_data_r <= data_r[3];
			end		
			4'h4:
			begin
				read_data_r <= data_r[4];
			end
				
			4'h5:
			begin
				read_data_r <= data_r[5];
			end
				
			4'h6:
			begin
				read_data_r <= data_r[6];
			end
			
			4'h7:
			begin
				read_data_r <= data_r[7];
			end		
			
			4'h8:
			begin
				read_data_r <= {7'h0,enable_r};
			end			
			default:
			begin
				read_data_r <= 8'h0;
			end
		endcase
	end
	else
		read_data_r <= 8'h0;
end


always @(posedge clock)
begin
	if (~reset_n)
	begin
		seven_segdisp_cnt <= 18'h0;
		data_addr <= 3'h0;
	end
	else
    begin
		seven_segdisp_cnt <= seven_segdisp_cnt + 18'h1;
		if(seven_segdisp_cnt >= 120000)
		begin
			data_addr <=  data_addr + 3'h1;
			seven_segdisp_cnt <= 18'h0;
		end
	end
end


always @(posedge clock)
begin
	if(~write_act)
	begin
		seg_data_r   <=  data_r[data_addr];
		seven_segdisp_addr_r <=  data_addr;
	end
end

assign seven_segdisp_addr = seven_segdisp_addr_r;
assign seg_data = seg_data_r;
assign seven_segdisp_enable = enable_r;
assign read_data = {24'h0,read_data_r};

endmodule