cymometer_task_logic.v

华清远见 高级的培训 实验代码

/****************************************Copyright (c)**************************************************
**                               Guangzhou ZHIYUAN ELECTRONIC CO.,LTD.
**                                      Research centre
**                         http://www.zyinside.com, http://www.zlgmcu.com
**
**---------------------------------------File Info-----------------------------------------------------
** File name:			cymometer_task_logic.v
** Last modified Date:	2006-02-23
** Last Version:		1.0
** Descriptions:		cymometer logic
**------------------------------------------------------------------------------------------------------
** Created by:			Zhous Shuwu
** Created date:		2006-02-23
** Version:				1.0
** Descriptions:		The original version
**
**------------------------------------------------------------------------------------------------------
** Modified by:			
** Modified date:		
** Version:				
** Descriptions:		
**
**------------------------------------------------------------------------------------------------------
********************************************************************************************************/

module cymometer_task_logic(
	clock,
	reset_n, 
	clock_divide,
	freq_input,
	freq_result
	);

	//Inputs
	input clock;				//Input Clock to be divided
	input [31:0] clock_divide;	//Clock Divide value
	input reset_n;				//Reset
	input freq_input;            //input frequence
	
	output [31:0] freq_result;    // output frequence

//Signal Declarations	
reg [31:0] counter;		   	   //Internal Counter
reg [31:0] freq_result_r;	   //output frequence register
reg [31:0] pre_freq;           //frequence temporary register
reg		   divide_clk;
	
//clock divide Process
always @(posedge clock or negedge reset_n)         
begin
	if (~reset_n)
	begin
		counter <= 32'h0;
		divide_clk <=1'h0;
	end
	else 
	begin
		if (counter < clock_divide)
 	    begin
 	    	counter <= counter + 32'h1;
 	    	divide_clk <= 1'b0;
 	    end
 	    else
 	    begin
 	    	counter <= 32'h0;
 	    	divide_clk <= 1'b1;
 	    end
 	end
end

always @(posedge divide_clk or negedge reset_n)       
begin
	if (~reset_n)
		freq_result_r <= 32'h0;
	else if (divide_clk)
		freq_result_r <= pre_freq;
	else
	    freq_result_r <= freq_result_r;
end

// frequence measure process
always @(posedge freq_input or posedge divide_clk or negedge reset_n)
begin
	if((~reset_n) | divide_clk )
	begin
		pre_freq <= 32'h0;    //clear the pre_freq
	end
	else
	begin
		pre_freq <= pre_freq + 32'h1;
	end
end

assign freq_result = freq_result_r;

endmodule