pwm_register_file.v

这个是华清远见 高级班 培训的 实验 代码

/****************************************Copyright (c)**************************************************
**                               Guangzhou ZHIYUAN ELECTRONIC CO.,LTD.
**                                      Research centre
**                         http://www.zyinside.com, http://www.zlgmcu.com
**
**---------------------------------------File Info-----------------------------------------------------
** File name:			pwm_register_file.v
** Last modified Date:	2005-12-13
** Last Version:		1.0
** Descriptions:		PWM logic
**------------------------------------------------------------------------------------------------------
** Created by:			LiuYingbin
** Created date:		2005-12-13
** Version:				1.0
** Descriptions:		The original version
**
**------------------------------------------------------------------------------------------------------
** Modified by:			
** Modified date:		
** Version:				
** Descriptions:		
**
**------------------------------------------------------------------------------------------------------
********************************************************************************************************/

module pwm_register_file(	
	//Avalon Signals
	clock,
	reset_n, 
	chip_select,
	address,
	write,
	write_data,
	read,
	read_data,

	//PWM Output Signals
	pwm_clock_divide,
	pwm_duty_cycle,
	pwm_enable
);

//Parameters
parameter clock_divide_reg_init = 32'h0000_0000;
parameter duty_cycle_reg_init   = 32'h0000_0000;

		input 			clock;			    //System Clock
		input 			reset_n;			//System Reset
		input 			chip_select;		//Avalon Chip select signal
		input [1:0] 	address;	     	//Avalon Address bus 
		input 			write;				//Avalon Write signal
		input [31:0] 	write_data;			//Avalon Write data bus
		input 			read;			    //Avalon read signal
		output [31:0] 	read_data;	  		//Avalon read data bus

		output [31:0] 	pwm_clock_divide; 	//PWM clock divide drive signals
		output [31:0] 	pwm_duty_cycle;   	//PWM duty cycle drive signals
		output        	pwm_enable;       	//PWM enable drive signals

//Signal Declarations	
reg [31:0] 	clock_divide_r;		//Clock divider register
reg [31:0] 	duty_cycle_r;  		//Duty Cycle Register
reg        	enable_r;	 		//Enable Bit	
reg [31:0] 	read_data_r;			//Read_data bus
wire		write_act,read_act;


//determine if a vaild transaction was initiated 
assign write_act = chip_select & write;		
assign read_act  = chip_select & read;

parameter		clock_divide	= 2'h0,
				duty_cycle		= 2'h1,
				enable_ctrl		= 2'h2;

//write
always @(posedge clock or negedge reset_n)
begin
	if (~reset_n)
	begin
		//initializtion
		clock_divide_r <= clock_divide_reg_init;
		duty_cycle_r <= duty_cycle_reg_init;
		enable_r <= 1'b0;
	end
	else if (write_act)
	begin
		case (address)
			clock_divide:
			begin
				clock_divide_r <= write_data;
			end
			
			duty_cycle:
			begin
				duty_cycle_r <= write_data;
			end
			
			enable_ctrl:
			begin
				enable_r <= write_data[0];
			end
			
			default:
			begin
			end
		endcase
	end
end

always @(read_act or address or clock_divide_r or duty_cycle_r or enable_r)
begin
	if (read_act)
	begin
		case (address)
				clock_divide:
				begin
					read_data_r <= clock_divide_r;
				end
				
				duty_cycle:
				begin
					read_data_r <= duty_cycle_r;
				end
				
				enable_ctrl:
				begin
					read_data_r <= {31'h0,enable_r};
				end	
				
				default:
				begin
					read_data_r <= 32'h0;
				end
		endcase
	end
	else
		read_data_r <= 32'h0;
end


assign pwm_clock_divide = clock_divide_r;
assign pwm_duty_cycle = duty_cycle_r;
assign pwm_enable = enable_r;

assign read_data = read_data_r;

endmodule