seven_segdisp_avalon_interface.v

这个是华清远见 高级班 培训的 实验 代码

/****************************************Copyright (c)**************************************************
**                               Guangzhou ZHIYUAN ELECTRONIC CO.,LTD.
**                                      Research centre
**                         http://www.zyinside.com, http://www.zlgmcu.com
**
**---------------------------------------File Info-----------------------------------------------------
** File name:			seven_segdisp_avalon_interface.v
** Last modified Date:	2005-12-13
** Last Version:		1.0
** Descriptions:		seven_segdisp avalon interface
**------------------------------------------------------------------------------------------------------
** Created by:			zhangjing
** Created date:		2006-02-14
** Version:				1.0
** Descriptions:		The original version
**
**------------------------------------------------------------------------------------------------------
** Modified by:			
** Modified date:		
** Version:				
** Descriptions:		
**
**------------------------------------------------------------------------------------------------------
********************************************************************************************************/


module seven_segdisp_avalon_interface(
	//Avalon Signals
	clock,
	reset_n,
	chip_select,
	address,
	write,
	write_data,
	read,
	read_data,
	
	//seven_segdisp Output Signals
	seg_code,
	digit_cs
 );

		//Avalon_Slave_seven_segdisp Avalon I/O
		input 			clock;		 	//System clock - tied to all blocks
		input 			reset_n;		//System reset - tied to all blocks
		input 			chip_select;	//Avalon Chip select
		input [3:0]		address;	    //Avalon Address bus 
		input 			write;			//Avalon Write signal
		input [31:0]	write_data;		//Avalon Write data bus
		input 			read;		    //Avalon Read signal
			
		output [31:0]	read_data;		//Avalon Read data bus
		
		//Avalon_Slave_seven_segdisp Exported I/O
		output[7:0] 	seg_code;		//segment code
		output[7:0]     digit_cs;       //digit choose
	
wire      seven_segdisp_enable;       	//seven_segdisp enable signal from register file
wire[7:0] seg_data;
wire[7:0] seven_segdisp_addr;	

reg[7:0]  seg_code;
reg[7:0]  digit_cs;
//Register File instance
seven_segdisp_register_file U1
(	
		.clock(clock),
		.reset_n(reset_n),
		.chip_select(chip_select),
		.address(address),
		.write(write),
		.write_data(write_data),
		.read(read),
		.read_data(read_data),
		//********************
		.seg_data(seg_data),
		.seven_segdisp_addr(seven_segdisp_addr),
		.seven_segdisp_enable(seven_segdisp_enable)
		);
//address translator instance
addr_trans U2
(
	.addr(seven_segdisp_addr),
	.seven_segdisp_enable(seven_segdisp_enable),
	.digit_cs(digit_cs)
);

//seven segment translator instance
seg_trans U3
(
	.data(seg_data),
	.seven_segdisp_enable(seven_segdisp_enable),
	.seg_code(seg_code)
);
endmodule