📄 niso2_1c6.ptf
字号:
name = "F_vinst";
radix = "ascii";
}
SIGNAL aas
{
format = "Logic";
name = "D_vinst";
radix = "ascii";
}
SIGNAL aat
{
format = "Logic";
name = "R_vinst";
radix = "ascii";
}
SIGNAL aau
{
format = "Logic";
name = "E_vinst";
radix = "ascii";
}
SIGNAL aav
{
format = "Logic";
name = "W_vinst";
radix = "ascii";
}
SIGNAL aaw
{
format = "Logic";
name = "F_valid";
radix = "hexadecimal";
}
SIGNAL aax
{
format = "Logic";
name = "D_valid";
radix = "hexadecimal";
}
SIGNAL aay
{
format = "Logic";
name = "R_valid";
radix = "hexadecimal";
}
SIGNAL aaz
{
format = "Logic";
name = "E_valid";
radix = "hexadecimal";
}
SIGNAL aba
{
format = "Logic";
name = "W_valid";
radix = "hexadecimal";
}
SIGNAL abb
{
format = "Logic";
name = "D_wr_dst_reg";
radix = "hexadecimal";
}
SIGNAL abc
{
format = "Logic";
name = "D_dst_regnum";
radix = "hexadecimal";
}
SIGNAL abd
{
format = "Logic";
name = "W_wr_data";
radix = "hexadecimal";
}
SIGNAL abe
{
format = "Logic";
name = "F_iw";
radix = "hexadecimal";
}
SIGNAL abf
{
format = "Logic";
name = "D_iw";
radix = "hexadecimal";
}
SIGNAL abg
{
format = "Divider";
name = "breaks";
radix = "";
}
SIGNAL abh
{
format = "Logic";
name = "hbreak_req";
radix = "hexadecimal";
}
SIGNAL abi
{
format = "Logic";
name = "oci_hbreak_req";
radix = "hexadecimal";
}
SIGNAL abj
{
format = "Logic";
name = "hbreak_enabled";
radix = "hexadecimal";
}
SIGNAL abk
{
format = "Logic";
name = "wait_for_one_post_bret_inst";
radix = "hexadecimal";
}
}
}
}
MODULE jtag_uart
{
class = "altera_avalon_jtag_uart";
class_version = "1.0";
iss_model_name = "altera_avalon_jtag_uart";
SLAVE avalon_jtag_slave
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Is_Printable_Device = "1";
Address_Alignment = "native";
Address_Width = "1";
Data_Width = "32";
Has_IRQ = "1";
Read_Wait_States = "peripheral_controlled";
Write_Wait_States = "peripheral_controlled";
JTAG_Hub_Base_Id = "0x04006E";
JTAG_Hub_Instance_Id = "0";
Connection_Limit = "1";
MASTERED_BY cpu/data_master
{
priority = "1";
}
IRQ_MASTER cpu/data_master
{
IRQ_Number = "0";
}
Base_Address = "0x00B00A00";
}
PORT_WIRING
{
PORT clk
{
type = "clk";
direction = "input";
width = "1";
Is_Enabled = "1";
}
PORT rst_n
{
type = "reset_n";
direction = "input";
width = "1";
Is_Enabled = "1";
}
PORT av_chipselect
{
type = "chipselect";
direction = "input";
width = "1";
Is_Enabled = "1";
}
PORT av_address
{
type = "address";
direction = "input";
width = "1";
Is_Enabled = "1";
}
PORT av_read_n
{
type = "read_n";
direction = "input";
width = "1";
Is_Enabled = "1";
}
PORT av_readdata
{
type = "readdata";
direction = "output";
width = "32";
Is_Enabled = "1";
}
PORT av_write_n
{
type = "write_n";
direction = "input";
width = "1";
Is_Enabled = "1";
}
PORT av_writedata
{
type = "writedata";
direction = "input";
width = "32";
Is_Enabled = "1";
}
PORT av_waitrequest
{
type = "waitrequest";
direction = "output";
width = "1";
Is_Enabled = "1";
}
PORT av_irq
{
type = "irq";
direction = "output";
width = "1";
Is_Enabled = "1";
}
PORT dataavailable
{
Is_Enabled = "1";
direction = "output";
type = "dataavailable";
width = "1";
}
PORT readyfordata
{
Is_Enabled = "1";
direction = "output";
type = "readyfordata";
width = "1";
}
}
}
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "1";
Is_Enabled = "1";
Iss_Launch_Telnet = "0";
Top_Level_Ports_Are_Enumerated = "1";
Clock_Source = "clk";
View
{
Settings_Summary = "<br>Write Depth: 64; Write IRQ Threshold: 8
<br>Read Depth: 64; Read IRQ Threshold: 8";
MESSAGES
{
}
Is_Collapsed = "1";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
write_depth = "64";
read_depth = "64";
write_threshold = "8";
read_threshold = "8";
read_char_stream = "";
showascii = "1";
read_le = "0";
write_le = "0";
}
SIMULATION
{
Fix_Me_Up = "";
DISPLAY
{
SIGNAL av_chipselect
{
name = "av_chipselect";
}
SIGNAL av_address
{
name = "av_address";
radix = "hexadecimal";
}
SIGNAL av_read_n
{
name = "av_read_n";
}
SIGNAL av_readdata
{
name = "av_readdata";
radix = "hexadecimal";
}
SIGNAL av_write_n
{
name = "av_write_n";
}
SIGNAL av_writedata
{
name = "av_writedata";
radix = "hexadecimal";
}
SIGNAL av_waitrequest
{
name = "av_waitrequest";
}
SIGNAL av_irq
{
name = "av_irq";
}
SIGNAL dataavailable
{
name = "dataavailable";
}
SIGNAL readyfordata
{
name = "readyfordata";
}
}
INTERACTIVE_IN drive
{
enable = "0";
file = "_input_data_stream.dat";
mutex = "_input_data_mutex.dat";
log = "_in.log";
rate = "100";
signals = "temp,list";
exe = "nios2-terminal";
}
INTERACTIVE_OUT log
{
enable = "1";
exe = "perl -- atail-f.pl";
file = "_output_stream.dat";
radix = "ascii";
signals = "temp,list";
}
}
HDL_INFO
{
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/jtag_uart.v";
Synthesis_Only_Files = "";
}
PORT_WIRING
{
}
}
MODULE uart
{
class = "altera_avalon_uart";
class_version = "4.2";
iss_model_name = "altera_avalon_uart";
PORT_WIRING
{
PORT rxd
{
direction = "input";
width = "1";
Is_Enabled = "1";
}
PORT txd
{
direction = "output";
width = "1";
Is_Enabled = "1";
}
PORT cts_n
{
direction = "input";
width = "1";
Is_Enabled = "0";
}
PORT rts_n
{
direction = "output";
width = "1";
Is_Enabled = "0";
}
}
SLAVE s1
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Is_Printable_Device = "1";
Address_Alignment = "native";
Address_Width = "3";
Data_Width = "16";
Has_IRQ = "1";
Read_Wait_States = "1";
Write_Wait_States = "1";
MASTERED_BY cpu/data_master
{
priority = "1";
}
IRQ_MASTER cpu/data_master
{
IRQ_Number = "1";
}
Base_Address = "0x00B00840";
}
PORT_WIRING
{
PORT address
{
Is_Enabled = "1";
direction = "input";
type = "address";
width = "3";
}
PORT begintransfer
{
Is_Enabled = "1";
direction = "input";
type = "begintransfer";
width = "1";
}
PORT chipselect
{
Is_Enabled = "1";
direction = "input";
type = "chipselect";
width = "1";
}
PORT clk
{
Is_Enabled = "1";
direction = "input";
type = "clk";
width = "1";
}
PORT dataavailable
{
Is_Enabled = "1";
direction = "output";
type = "dataavailable";
width = "1";
}
PORT irq
{
Is_Enabled = "1";
direction = "output";
type = "irq";
width = "1";
}
PORT read_n
{
Is_Enabled = "1";
direction = "input";
type = "read_n";
width = "1";
}
PORT readdata
{
Is_Enabled = "1";
direction = "output";
type = "readdata";
width = "16";
}
PORT readyfordata
{
Is_Enabled = "1";
direction = "output";
type = "readyfordata";
width = "1";
}
PORT reset_n
{
Is_Enabled = "1";
direction = "input";
type = "reset_n";
width = "1";
}
PORT write_n
{
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