niso2_1c6.v

这个是华清远见 高级班 培训的 实验 代码

                                cpu_data_master_address_to_slave,
                                cpu_data_master_read,
                                cpu_data_master_waitrequest,
                                cpu_data_master_write,
                                cpu_data_master_writedata,
                                reset_n,

                               // outputs:
                                adc_pio_s1_address,
                                adc_pio_s1_chipselect,
                                adc_pio_s1_readdata_from_sa,
                                adc_pio_s1_reset_n,
                                adc_pio_s1_write_n,
                                adc_pio_s1_writedata,
                                cpu_data_master_granted_adc_pio_s1,
                                cpu_data_master_qualified_request_adc_pio_s1,
                                cpu_data_master_read_data_valid_adc_pio_s1,
                                cpu_data_master_requests_adc_pio_s1,
                                d1_adc_pio_s1_end_xfer
                             );

  output  [  1: 0] adc_pio_s1_address;
  output           adc_pio_s1_chipselect;
  output  [  2: 0] adc_pio_s1_readdata_from_sa;
  output           adc_pio_s1_reset_n;
  output           adc_pio_s1_write_n;
  output  [  2: 0] adc_pio_s1_writedata;
  output           cpu_data_master_granted_adc_pio_s1;
  output           cpu_data_master_qualified_request_adc_pio_s1;
  output           cpu_data_master_read_data_valid_adc_pio_s1;
  output           cpu_data_master_requests_adc_pio_s1;
  output           d1_adc_pio_s1_end_xfer;
  input   [  2: 0] adc_pio_s1_readdata;
  input            clk;
  input   [ 23: 0] cpu_data_master_address_to_slave;
  input            cpu_data_master_read;
  input            cpu_data_master_waitrequest;
  input            cpu_data_master_write;
  input   [ 31: 0] cpu_data_master_writedata;
  input            reset_n;

  wire    [  1: 0] adc_pio_s1_address;
  wire             adc_pio_s1_allgrants;
  wire             adc_pio_s1_allow_new_arb_cycle;
  wire             adc_pio_s1_any_continuerequest;
  wire             adc_pio_s1_arb_counter_enable;
  reg     [  1: 0] adc_pio_s1_arb_share_counter;
  wire    [  1: 0] adc_pio_s1_arb_share_counter_next_value;
  wire    [  1: 0] adc_pio_s1_arb_share_set_values;
  wire             adc_pio_s1_arbitration_holdoff_internal;
  wire             adc_pio_s1_beginbursttransfer_internal;
  wire             adc_pio_s1_begins_xfer;
  wire             adc_pio_s1_chipselect;
  wire             adc_pio_s1_end_xfer;
  wire             adc_pio_s1_firsttransfer;
  wire             adc_pio_s1_grant_vector;
  wire             adc_pio_s1_in_a_read_cycle;
  wire             adc_pio_s1_in_a_write_cycle;
  wire             adc_pio_s1_master_qreq_vector;
  wire    [  2: 0] adc_pio_s1_readdata_from_sa;
  wire             adc_pio_s1_reset_n;
  reg              adc_pio_s1_slavearbiterlockenable;
  wire             adc_pio_s1_waits_for_read;
  wire             adc_pio_s1_waits_for_write;
  wire             adc_pio_s1_write_n;
  wire    [  2: 0] adc_pio_s1_writedata;
  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_adc_pio_s1;
  wire             cpu_data_master_qualified_request_adc_pio_s1;
  wire             cpu_data_master_read_data_valid_adc_pio_s1;
  wire             cpu_data_master_requests_adc_pio_s1;
  wire             cpu_data_master_saved_grant_adc_pio_s1;
  reg              d1_adc_pio_s1_end_xfer;
  reg              d1_reasons_to_wait;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             wait_for_adc_pio_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else if (1)
          d1_reasons_to_wait <= ~adc_pio_s1_end_xfer;
    end


  assign adc_pio_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_adc_pio_s1));
  //assign adc_pio_s1_readdata_from_sa = adc_pio_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign adc_pio_s1_readdata_from_sa = adc_pio_s1_readdata;

  assign cpu_data_master_requests_adc_pio_s1 = ({cpu_data_master_address_to_slave[23 : 4] , 4'b0} == 24'hb009e0) & (cpu_data_master_read | cpu_data_master_write);
  //adc_pio_s1_arb_share_counter set values, which is an e_mux
  assign adc_pio_s1_arb_share_set_values = 1;

  //adc_pio_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign adc_pio_s1_arb_share_counter_next_value = adc_pio_s1_firsttransfer ? (adc_pio_s1_arb_share_set_values - 1) : |adc_pio_s1_arb_share_counter ? (adc_pio_s1_arb_share_counter - 1) : 0;

  //adc_pio_s1_allgrants all slave grants, which is an e_mux
  assign adc_pio_s1_allgrants = |adc_pio_s1_grant_vector;

  //adc_pio_s1_end_xfer assignment, which is an e_assign
  assign adc_pio_s1_end_xfer = ~(adc_pio_s1_waits_for_read | adc_pio_s1_waits_for_write);

  //adc_pio_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign adc_pio_s1_arb_counter_enable = adc_pio_s1_end_xfer & adc_pio_s1_allgrants;

  //adc_pio_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          adc_pio_s1_arb_share_counter <= 0;
      else if (adc_pio_s1_arb_counter_enable)
          adc_pio_s1_arb_share_counter <= adc_pio_s1_arb_share_counter_next_value;
    end


  //adc_pio_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          adc_pio_s1_slavearbiterlockenable <= 0;
      else if (|adc_pio_s1_master_qreq_vector & adc_pio_s1_end_xfer)
          adc_pio_s1_slavearbiterlockenable <= |adc_pio_s1_arb_share_counter_next_value;
    end


  //cpu/data_master adc_pio/s1 arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = adc_pio_s1_slavearbiterlockenable & cpu_data_master_continuerequest;

  //adc_pio_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign adc_pio_s1_any_continuerequest = 0;

  //cpu_data_master_continuerequest continued request, which is an e_assign
  assign cpu_data_master_continuerequest = 0;

  assign cpu_data_master_qualified_request_adc_pio_s1 = cpu_data_master_requests_adc_pio_s1 & ~(((~cpu_data_master_waitrequest) & cpu_data_master_write));
  //adc_pio_s1_writedata mux, which is an e_mux
  assign adc_pio_s1_writedata = cpu_data_master_writedata;

  //master is always granted when requested
  assign cpu_data_master_granted_adc_pio_s1 = cpu_data_master_qualified_request_adc_pio_s1;

  //cpu/data_master saved-grant adc_pio/s1, which is an e_assign
  assign cpu_data_master_saved_grant_adc_pio_s1 = cpu_data_master_requests_adc_pio_s1;

  //allow new arb cycle for adc_pio/s1, which is an e_assign
  assign adc_pio_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign adc_pio_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign adc_pio_s1_master_qreq_vector = 1;

  //adc_pio_s1_reset_n assignment, which is an e_assign
  assign adc_pio_s1_reset_n = reset_n;

  assign adc_pio_s1_chipselect = cpu_data_master_granted_adc_pio_s1;
  //adc_pio_s1_firsttransfer first transaction, which is an e_assign
  assign adc_pio_s1_firsttransfer = ~(adc_pio_s1_slavearbiterlockenable & adc_pio_s1_any_continuerequest);

  //adc_pio_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign adc_pio_s1_beginbursttransfer_internal = adc_pio_s1_begins_xfer & adc_pio_s1_firsttransfer;

  //adc_pio_s1_arbitration_holdoff_internal arbitration_holdoff, which is an e_assign
  assign adc_pio_s1_arbitration_holdoff_internal = adc_pio_s1_begins_xfer & adc_pio_s1_firsttransfer;

  //~adc_pio_s1_write_n assignment, which is an e_mux
  assign adc_pio_s1_write_n = ~(cpu_data_master_granted_adc_pio_s1 & cpu_data_master_write);

  //adc_pio_s1_address mux, which is an e_mux
  assign adc_pio_s1_address = cpu_data_master_address_to_slave >> 2;

  //d1_adc_pio_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_adc_pio_s1_end_xfer <= 1;
      else if (1)
          d1_adc_pio_s1_end_xfer <= adc_pio_s1_end_xfer;
    end


  //adc_pio_s1_waits_for_read in a cycle, which is an e_mux
  assign adc_pio_s1_waits_for_read = adc_pio_s1_in_a_read_cycle & adc_pio_s1_begins_xfer;

  //adc_pio_s1_in_a_read_cycle assignment, which is an e_assign
  assign adc_pio_s1_in_a_read_cycle = cpu_data_master_granted_adc_pio_s1 & cpu_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = adc_pio_s1_in_a_read_cycle;

  //adc_pio_s1_waits_for_write in a cycle, which is an e_mux
  assign adc_pio_s1_waits_for_write = adc_pio_s1_in_a_write_cycle & 0;

  //adc_pio_s1_in_a_write_cycle assignment, which is an e_assign
  assign adc_pio_s1_in_a_write_cycle = cpu_data_master_granted_adc_pio_s1 & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = adc_pio_s1_in_a_write_cycle;

  assign wait_for_adc_pio_s1_counter = 0;

  // synthesis attribute adc_pio_s1_arbitrator auto_dissolve FALSE

endmodule


module beep_pwm_control_slave_arbitrator (
                                           // inputs:
                                            beep_pwm_control_slave_readdata,
                                            clk,
                                            cpu_data_master_address_to_slave,
                                            cpu_data_master_read,
                                            cpu_data_master_waitrequest,
                                            cpu_data_master_write,
                                            cpu_data_master_writedata,
                                            reset_n,

                                           // outputs:
                                            beep_pwm_control_slave_address,
                                            beep_pwm_control_slave_chipselect,
                                            beep_pwm_control_slave_read,
                                            beep_pwm_control_slave_readdata_from_sa,
                                            beep_pwm_control_slave_reset_n,
                                            beep_pwm_control_slave_write,
                                            beep_pwm_control_slave_writedata,
                                            cpu_data_master_granted_beep_pwm_control_slave,
                                            cpu_data_master_qualified_request_beep_pwm_control_slave,
                                            cpu_data_master_read_data_valid_beep_pwm_control_slave,