niso2_1c6.v

这个是华清远见 高级班 培训的 实验 代码

//megafunction wizard: %Altera SOPC Builder%
//GENERATION: STANDARD
//VERSION: WM1.0


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// synthesis translate_off
`timescale 1ns / 100ps
// synthesis translate_on
module DcMotorA_pwm_control_slave_arbitrator (
                                               // inputs:
                                                DcMotorA_pwm_control_slave_readdata,
                                                clk,
                                                cpu_data_master_address_to_slave,
                                                cpu_data_master_read,
                                                cpu_data_master_waitrequest,
                                                cpu_data_master_write,
                                                cpu_data_master_writedata,
                                                reset_n,

                                               // outputs:
                                                DcMotorA_pwm_control_slave_address,
                                                DcMotorA_pwm_control_slave_chipselect,
                                                DcMotorA_pwm_control_slave_read,
                                                DcMotorA_pwm_control_slave_readdata_from_sa,
                                                DcMotorA_pwm_control_slave_reset_n,
                                                DcMotorA_pwm_control_slave_write,
                                                DcMotorA_pwm_control_slave_writedata,
                                                cpu_data_master_granted_DcMotorA_pwm_control_slave,
                                                cpu_data_master_qualified_request_DcMotorA_pwm_control_slave,
                                                cpu_data_master_read_data_valid_DcMotorA_pwm_control_slave,
                                                cpu_data_master_requests_DcMotorA_pwm_control_slave,
                                                d1_DcMotorA_pwm_control_slave_end_xfer
                                             );

  output  [  1: 0] DcMotorA_pwm_control_slave_address;
  output           DcMotorA_pwm_control_slave_chipselect;
  output           DcMotorA_pwm_control_slave_read;
  output  [ 31: 0] DcMotorA_pwm_control_slave_readdata_from_sa;
  output           DcMotorA_pwm_control_slave_reset_n;
  output           DcMotorA_pwm_control_slave_write;
  output  [ 31: 0] DcMotorA_pwm_control_slave_writedata;
  output           cpu_data_master_granted_DcMotorA_pwm_control_slave;
  output           cpu_data_master_qualified_request_DcMotorA_pwm_control_slave;
  output           cpu_data_master_read_data_valid_DcMotorA_pwm_control_slave;
  output           cpu_data_master_requests_DcMotorA_pwm_control_slave;
  output           d1_DcMotorA_pwm_control_slave_end_xfer;
  input   [ 31: 0] DcMotorA_pwm_control_slave_readdata;
  input            clk;
  input   [ 23: 0] cpu_data_master_address_to_slave;
  input            cpu_data_master_read;
  input            cpu_data_master_waitrequest;
  input            cpu_data_master_write;
  input   [ 31: 0] cpu_data_master_writedata;
  input            reset_n;

  wire    [  1: 0] DcMotorA_pwm_control_slave_address;
  wire             DcMotorA_pwm_control_slave_allgrants;
  wire             DcMotorA_pwm_control_slave_allow_new_arb_cycle;
  wire             DcMotorA_pwm_control_slave_any_continuerequest;
  wire             DcMotorA_pwm_control_slave_arb_counter_enable;
  reg     [  1: 0] DcMotorA_pwm_control_slave_arb_share_counter;
  wire    [  1: 0] DcMotorA_pwm_control_slave_arb_share_counter_next_value;
  wire    [  1: 0] DcMotorA_pwm_control_slave_arb_share_set_values;
  wire             DcMotorA_pwm_control_slave_arbitration_holdoff_internal;
  wire             DcMotorA_pwm_control_slave_beginbursttransfer_internal;
  wire             DcMotorA_pwm_control_slave_begins_xfer;
  wire             DcMotorA_pwm_control_slave_chipselect;
  wire             DcMotorA_pwm_control_slave_end_xfer;
  wire             DcMotorA_pwm_control_slave_firsttransfer;
  wire             DcMotorA_pwm_control_slave_grant_vector;
  wire             DcMotorA_pwm_control_slave_in_a_read_cycle;
  wire             DcMotorA_pwm_control_slave_in_a_write_cycle;
  wire             DcMotorA_pwm_control_slave_master_qreq_vector;
  wire             DcMotorA_pwm_control_slave_read;
  wire    [ 31: 0] DcMotorA_pwm_control_slave_readdata_from_sa;
  wire             DcMotorA_pwm_control_slave_reset_n;
  reg              DcMotorA_pwm_control_slave_slavearbiterlockenable;
  wire             DcMotorA_pwm_control_slave_waits_for_read;
  wire             DcMotorA_pwm_control_slave_waits_for_write;
  wire             DcMotorA_pwm_control_slave_write;
  wire    [ 31: 0] DcMotorA_pwm_control_slave_writedata;
  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_DcMotorA_pwm_control_slave;
  wire             cpu_data_master_qualified_request_DcMotorA_pwm_control_slave;
  wire             cpu_data_master_read_data_valid_DcMotorA_pwm_control_slave;
  wire             cpu_data_master_requests_DcMotorA_pwm_control_slave;
  wire             cpu_data_master_saved_grant_DcMotorA_pwm_control_slave;
  reg              d1_DcMotorA_pwm_control_slave_end_xfer;
  reg              d1_reasons_to_wait;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             wait_for_DcMotorA_pwm_control_slave_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else if (1)
          d1_reasons_to_wait <= ~DcMotorA_pwm_control_slave_end_xfer;
    end


  assign DcMotorA_pwm_control_slave_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_DcMotorA_pwm_control_slave));
  //assign DcMotorA_pwm_control_slave_readdata_from_sa = DcMotorA_pwm_control_slave_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign DcMotorA_pwm_control_slave_readdata_from_sa = DcMotorA_pwm_control_slave_readdata;

  assign cpu_data_master_requests_DcMotorA_pwm_control_slave = ({cpu_data_master_address_to_slave[23 : 4] , 4'b0} == 24'hb00960) & (cpu_data_master_read | cpu_data_master_write);
  //DcMotorA_pwm_control_slave_arb_share_counter set values, which is an e_mux
  assign DcMotorA_pwm_control_slave_arb_share_set_values = 1;

  //DcMotorA_pwm_control_slave_arb_share_counter_next_value assignment, which is an e_assign
  assign DcMotorA_pwm_control_slave_arb_share_counter_next_value = DcMotorA_pwm_control_slave_firsttransfer ? (DcMotorA_pwm_control_slave_arb_share_set_values - 1) : |DcMotorA_pwm_control_slave_arb_share_counter ? (DcMotorA_pwm_control_slave_arb_share_counter - 1) : 0;

  //DcMotorA_pwm_control_slave_allgrants all slave grants, which is an e_mux
  assign DcMotorA_pwm_control_slave_allgrants = |DcMotorA_pwm_control_slave_grant_vector;

  //DcMotorA_pwm_control_slave_end_xfer assignment, which is an e_assign
  assign DcMotorA_pwm_control_slave_end_xfer = ~(DcMotorA_pwm_control_slave_waits_for_read | DcMotorA_pwm_control_slave_waits_for_write);

  //DcMotorA_pwm_control_slave_arb_share_counter arbitration counter enable, which is an e_assign
  assign DcMotorA_pwm_control_slave_arb_counter_enable = DcMotorA_pwm_control_slave_end_xfer & DcMotorA_pwm_control_slave_allgrants;

  //DcMotorA_pwm_control_slave_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          DcMotorA_pwm_control_slave_arb_share_counter <= 0;
      else if (DcMotorA_pwm_control_slave_arb_counter_enable)
          DcMotorA_pwm_control_slave_arb_share_counter <= DcMotorA_pwm_control_slave_arb_share_counter_next_value;
    end


  //DcMotorA_pwm_control_slave_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          DcMotorA_pwm_control_slave_slavearbiterlockenable <= 0;
      else if (|DcMotorA_pwm_control_slave_master_qreq_vector & DcMotorA_pwm_control_slave_end_xfer)
          DcMotorA_pwm_control_slave_slavearbiterlockenable <= |DcMotorA_pwm_control_slave_arb_share_counter_next_value;
    end


  //cpu/data_master DcMotorA_pwm/control_slave arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = DcMotorA_pwm_control_slave_slavearbiterlockenable & cpu_data_master_continuerequest;

  //DcMotorA_pwm_control_slave_any_continuerequest at least one master continues requesting, which is an e_assign
  assign DcMotorA_pwm_control_slave_any_continuerequest = 0;

  //cpu_data_master_continuerequest continued request, which is an e_assign
  assign cpu_data_master_continuerequest = 0;

  assign cpu_data_master_qualified_request_DcMotorA_pwm_control_slave = cpu_data_master_requests_DcMotorA_pwm_control_slave & ~((cpu_data_master_read & (~cpu_data_master_waitrequest)) | ((~cpu_data_master_waitrequest) & cpu_data_master_write));
  //DcMotorA_pwm_control_slave_writedata mux, which is an e_mux
  assign DcMotorA_pwm_control_slave_writedata = cpu_data_master_writedata;

  //master is always granted when requested
  assign cpu_data_master_granted_DcMotorA_pwm_control_slave = cpu_data_master_qualified_request_DcMotorA_pwm_control_slave;

  //cpu/data_master saved-grant DcMotorA_pwm/control_slave, which is an e_assign
  assign cpu_data_master_saved_grant_DcMotorA_pwm_control_slave = cpu_data_master_requests_DcMotorA_pwm_control_slave;

  //allow new arb cycle for DcMotorA_pwm/control_slave, which is an e_assign
  assign DcMotorA_pwm_control_slave_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign DcMotorA_pwm_control_slave_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign DcMotorA_pwm_control_slave_master_qreq_vector = 1;

  //DcMotorA_pwm_control_slave_reset_n assignment, which is an e_assign
  assign DcMotorA_pwm_control_slave_reset_n = reset_n;

  assign DcMotorA_pwm_control_slave_chipselect = cpu_data_master_granted_DcMotorA_pwm_control_slave;
  //DcMotorA_pwm_control_slave_firsttransfer first transaction, which is an e_assign
  assign DcMotorA_pwm_control_slave_firsttransfer = ~(DcMotorA_pwm_control_slave_slavearbiterlockenable & DcMotorA_pwm_control_slave_any_continuerequest);

  //DcMotorA_pwm_control_slave_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign DcMotorA_pwm_control_slave_beginbursttransfer_internal = DcMotorA_pwm_control_slave_begins_xfer & DcMotorA_pwm_control_slave_firsttransfer;

  //DcMotorA_pwm_control_slave_arbitration_holdoff_internal arbitration_holdoff, which is an e_assign
  assign DcMotorA_pwm_control_slave_arbitration_holdoff_internal = DcMotorA_pwm_control_slave_begins_xfer & DcMotorA_pwm_control_slave_firsttransfer;

  //DcMotorA_pwm_control_slave_read assignment, which is an e_mux
  assign DcMotorA_pwm_control_slave_read = cpu_data_master_granted_DcMotorA_pwm_control_slave & cpu_data_master_read;

  //DcMotorA_pwm_control_slave_write assignment, which is an e_mux
  assign DcMotorA_pwm_control_slave_write = cpu_data_master_granted_DcMotorA_pwm_control_slave & cpu_data_master_write;

  //DcMotorA_pwm_control_slave_address mux, which is an e_mux
  assign DcMotorA_pwm_control_slave_address = cpu_data_master_address_to_slave >> 2;

  //d1_DcMotorA_pwm_control_slave_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_DcMotorA_pwm_control_slave_end_xfer <= 1;
      else if (1)
          d1_DcMotorA_pwm_control_slave_end_xfer <= DcMotorA_pwm_control_slave_end_xfer;
    end


  //DcMotorA_pwm_control_slave_waits_for_read in a cycle, which is an e_mux
  assign DcMotorA_pwm_control_slave_waits_for_read = DcMotorA_pwm_control_slave_in_a_read_cycle & 0;

  //DcMotorA_pwm_control_slave_in_a_read_cycle assignment, which is an e_assign
  assign DcMotorA_pwm_control_slave_in_a_read_cycle = cpu_data_master_granted_DcMotorA_pwm_control_slave & cpu_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = DcMotorA_pwm_control_slave_in_a_read_cycle;

  //DcMotorA_pwm_control_slave_waits_for_write in a cycle, which is an e_mux
  assign DcMotorA_pwm_control_slave_waits_for_write = DcMotorA_pwm_control_slave_in_a_write_cycle & 0;

  //DcMotorA_pwm_control_slave_in_a_write_cycle assignment, which is an e_assign
  assign DcMotorA_pwm_control_slave_in_a_write_cycle = cpu_data_master_granted_DcMotorA_pwm_control_slave & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = DcMotorA_pwm_control_slave_in_a_write_cycle;