tlc5620_register_file.v

这个是华清远见 高级班 培训的 实验 代码

/****************************************Copyright (c)**************************************************
**                               Guangzhou ZHIYUAN ELECTRONIC CO.,LTD.
**                                      Research centre
**                         http://www.zyinside.com, http://www.zlgmcu.com
**
**---------------------------------------File Info-----------------------------------------------------
** File name:			tlc5620_register_file.v
** Last modified Date:	2005-12-14
** Last Version:		1.0
** Descriptions:		tlc5620 register define
**------------------------------------------------------------------------------------------------------
** Created by:			ZhouShuwu
** Created date:		2005-12-14
** Version:				1.0
** Descriptions:		The original version
**
**------------------------------------------------------------------------------------------------------
** Modified by:			
** Modified date:		
** Version:				
** Descriptions:		
**
**------------------------------------------------------------------------------------------------------
********************************************************************************************************/

module tlc5620_register_file(	
	//Avalon Signals
	clock,
	reset_n, 
	chip_select,
	address,
	write,
	write_data,

	//tlc5620 Output Signals
	tlc5620_clock_divide,
	tlc5620_write_data,
	tlc5620_write_act
);
	
//Parameters
parameter clock_divide_reg_init = 32'h0000_0030;
parameter write_data_reg_init 	= 11'h000;

		input 			clock;			    //System Clock
		input 			reset_n;			//System Reset
		input 			chip_select;		//Avalon Chip select signal
		input[1:0]	 	address;	     	//Avalon Address bus 
		input 			write;				//Avalon Write signal
		input[31:0] 	write_data;			//Avalon Write data bus

		output [31:0] 	tlc5620_clock_divide; //tlc5620 clock divide drive signals
		output [10:0]	tlc5620_write_data;
		output        	tlc5620_write_act;    //tlc5620 write act drive signals

//Signal Declarations	
reg [31:0] 	clock_divide_r;		//Clock divider register
reg [10:0] 	write_data_r;  		//write data Register
reg			write_act_r;
wire		write_act;


//determine if a vaild transaction was initiated 
assign write_act = chip_select & write;		

parameter		clock_divide_reg	= 2'h0,
				write_data_reg		= 2'h1;

//write
always @(posedge clock or negedge reset_n)
begin
	if (~reset_n)
	begin
		//initializtion
		clock_divide_r <= clock_divide_reg_init;
		write_data_r <= write_data_reg_init;
		write_act_r <= 1'b0;
	end
	else if (write_act)
	begin		
		case (address)
			clock_divide_reg:
			begin				
				clock_divide_r <= write_data;
			end
			
			write_data_reg:
			begin
				write_act_r <= 1'b1;
				write_data_r <= write_data[10:0];
			end

			default:
			begin
			end
		endcase
	end
	else
		write_act_r <= 1'b0;
end

assign tlc5620_clock_divide = clock_divide_r;
assign tlc5620_write_data = write_data_r;
assign tlc5620_write_act = write_act_r;

endmodule