niso2_1c6.ptf.bak

这个是华清远见 高级班 培训的 实验 代码

            }
            PORT writedata
            {
               Is_Enabled = "1";
               direction = "input";
               type = "writedata";
               width = "16";
            }
         }
      }
      SYSTEM_BUILDER_INFO 
      {
         Instantiate_In_System_Module = "1";
         Is_Enabled = "1";
         Iss_Launch_Telnet = "0";
         Top_Level_Ports_Are_Enumerated = "1";
         Clock_Source = "clk";
         View 
         {
            Settings_Summary = "8-bit UART with 115200 baud, <br>
                    1 stop bits and N parity";
            MESSAGES 
            {
            }
            Is_Collapsed = "1";
         }
      }
      SIMULATION 
      {
         DISPLAY 
         {
            SIGNAL a
            {
               name = "  Bus Interface";
               format = "Divider";
            }
            SIGNAL b
            {
               name = "chipselect";
            }
            SIGNAL c
            {
               name = "address";
               radix = "hexadecimal";
            }
            SIGNAL d
            {
               name = "writedata";
               radix = "hexadecimal";
            }
            SIGNAL e
            {
               name = "readdata";
               radix = "hexadecimal";
            }
            SIGNAL f
            {
               name = "  Internals";
               format = "Divider";
            }
            SIGNAL g
            {
               name = "tx_ready";
            }
            SIGNAL h
            {
               name = "tx_data";
               radix = "ascii";
            }
            SIGNAL i
            {
               name = "rx_char_ready";
            }
            SIGNAL j
            {
               name = "rx_data";
               radix = "ascii";
            }
         }
         INTERACTIVE_OUT log
         {
            enable = "0";
            file = "_log_module.txt";
            radix = "ascii";
            signals = "temp,list";
            exe = "perl -- tail-f.pl";
         }
         INTERACTIVE_IN drive
         {
            enable = "0";
            file = "_input_data_stream.dat";
            mutex = "_input_data_mutex.dat";
            log = "_in.log";
            rate = "100";
            signals = "temp,list";
            exe = "perl -- uart.pl";
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         baud = "115200";
         data_bits = "8";
         fixed_baud = "0";
         parity = "N";
         stop_bits = "1";
         use_cts_rts = "0";
         use_eop_register = "0";
         sim_true_baud = "0";
         sim_char_stream = "";
      }
      HDL_INFO 
      {
         Precompiled_Simulation_Library_Files = "";
         Simulation_HDL_Files = "";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/uart.v";
         Synthesis_Only_Files = "";
      }
   }
   MODULE sdram
   {
      class = "altera_avalon_new_sdram_controller";
      class_version = "4.2";
      iss_model_name = "altera_memory";
      SLAVE s1
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Address_Alignment = "dynamic";
            Has_IRQ = "0";
            Maximum_Pending_Read_Transactions = "7";
            Read_Wait_States = "peripheral_controlled";
            Write_Wait_States = "peripheral_controlled";
            Is_Memory_Device = "1";
            Address_Width = "22";
            Data_Width = "16";
            Simulation_Num_Lanes = "1";
            MASTERED_BY cpu/instruction_master
            {
               priority = "1";
            }
            MASTERED_BY cpu/data_master
            {
               priority = "1";
            }
            Base_Address = "0x00800000";
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "NC";
            }
         }
         PORT_WIRING 
         {
            PORT zs_addr
            {
               direction = "output";
               width = "12";
               Is_Enabled = "1";
            }
            PORT zs_ba
            {
               direction = "output";
               width = "2";
               Is_Enabled = "1";
            }
            PORT zs_cas_n
            {
               direction = "output";
               width = "1";
               Is_Enabled = "1";
            }
            PORT zs_cke
            {
               direction = "output";
               width = "1";
               Is_Enabled = "1";
            }
            PORT zs_cs_n
            {
               direction = "output";
               width = "1";
               Is_Enabled = "1";
            }
            PORT zs_dq
            {
               direction = "inout";
               width = "16";
               Is_Enabled = "1";
            }
            PORT zs_dqm
            {
               direction = "output";
               width = "2";
               Is_Enabled = "1";
            }
            PORT zs_ras_n
            {
               direction = "output";
               width = "1";
               Is_Enabled = "1";
            }
            PORT zs_we_n
            {
               direction = "output";
               width = "1";
               Is_Enabled = "1";
            }
            PORT az_addr
            {
               Is_Enabled = "1";
               direction = "input";
               type = "address";
               width = "22";
            }
            PORT az_be_n
            {
               Is_Enabled = "1";
               direction = "input";
               type = "byteenable_n";
               width = "2";
            }
            PORT az_cs
            {
               Is_Enabled = "1";
               direction = "input";
               type = "chipselect";
               width = "1";
            }
            PORT az_data
            {
               Is_Enabled = "1";
               direction = "input";
               type = "writedata";
               width = "16";
            }
            PORT az_rd_n
            {
               Is_Enabled = "1";
               direction = "input";
               type = "read_n";
               width = "1";
            }
            PORT az_wr_n
            {
               Is_Enabled = "1";
               direction = "input";
               type = "write_n";
               width = "1";
            }
            PORT clk
            {
               Is_Enabled = "1";
               direction = "input";
               type = "clk";
               width = "1";
            }
            PORT reset_n
            {
               Is_Enabled = "1";
               direction = "input";
               type = "reset_n";
               width = "1";
            }
            PORT za_data
            {
               Is_Enabled = "1";
               direction = "output";
               type = "readdata";
               width = "16";
            }
            PORT za_valid
            {
               Is_Enabled = "1";
               direction = "output";
               type = "readdatavalid";
               width = "1";
            }
            PORT za_waitrequest
            {
               Is_Enabled = "1";
               direction = "output";
               type = "waitrequest";
               width = "1";
            }
         }
      }
      SYSTEM_BUILDER_INFO 
      {
         Instantiate_In_System_Module = "1";
         Is_Enabled = "1";
         Default_Module_Name = "sdram";
         Disable_Simulation_Port_Wiring = "0";
         Top_Level_Ports_Are_Enumerated = "1";
         Clock_Source = "clk";
         View 
         {
            Settings_Summary = "4194304 x 16<br>
                Memory size: 8 MBytes<br>
                64 MBits
                ";
            MESSAGES 
            {
            }
            Is_Collapsed = "1";
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         register_data_in = "1";
         sim_model_base = "1";
         sdram_data_width = "16";
         sdram_addr_width = "12";
         sdram_row_width = "12";
         sdram_col_width = "8";
         sdram_num_chipselects = "1";
         sdram_num_banks = "4";
         refresh_period = "15.625";
         powerup_delay = "100";
         cas_latency = "3";
         t_rfc = "70";
         t_rp = "20";
         t_mrd = "3";
         t_rcd = "20";
         t_ac = "5.5";
         t_wr = "14";
         init_refresh_commands = "2";
         init_nop_delay = "0";
         shared_data = "0";
         starvation_indicator = "0";
         tristate_bridge_slave = "";
         is_initialized = "1";
         sdram_bank_width = "2";
         MAKE 
         {
            TARGET delete_placeholder_warning
            {
               sdram 
               {
                  Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt";
                  Is_Phony = "1";
                  Target_File = "do_delete_placeholder_warning";
               }
            }
            TARGET sim
            {
               sdram 
               {
                  Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";
                  Command2 = "@echo Hardware simulation is not enabled for the target SOPC Builder system. Skipping creation of hardware simulation model contents and simulation symbol files. \\(Note: This does not affect the instruction set simulator.\\)";
                  Command3 = "touch $(SIMDIR)/dummy_file";
                  Dependency = "$(ELF)";
                  Target_File = "$(SIMDIR)/dummy_file";
               }
            }
         }
      }
      SIMULATION 
      {
         Fix_Me_Up = "";
         DISPLAY 
         {
            SIGNAL a
            {
               name = "az_addr";
               radix = "hexadecimal";
            }
            SIGNAL b
            {
               name = "az_be_n";
               radix = "hexadecimal";
            }
            SIGNAL c
            {
               name = "az_cs";
            }
            SIGNAL d
            {
               name = "az_data";
               radix = "hexadecimal";
            }
            SIGNAL e
            {
               name = "az_rd_n";
            }
            SIGNAL f
            {
               name = "az_wr_n";
            }
            SIGNAL g
            {
               name = "clk";
            }
            SIGNAL h
            {
               name = "za_data";
               radix = "hexadecimal";
            }
            SIGNAL i
            {
               name = "za_valid";
            }
            SIGNAL j
            {
               name = "za_waitrequest";
            }
            SIGNAL k
            {
               name = "za_cannotrefresh";
               suppress = "1";
            }
            SIGNAL l
            {
               name = "CODE";
               radix = "ascii";
            }
            SIGNAL m
            {
               name = "zs_addr";
               radix = "hexadecimal";
               suppress = "0";
            }
            SIGNAL n
            {
               name = "zs_ba";
               radix = "hexadecimal";
               suppress = "0";
            }
            SIGNAL o
            {
               name = "zs_cs_n";
               radix = "hexadecimal";
               suppress = "0";
            }
            SIGNAL p
            {
               name = "zs_ras_n";
               suppress = "0";
            }
            SIGNAL q
            {
               name = "zs_cas_n";
               suppress = "0";
            }
            SIGNAL r
            {
               name = "zs_we_n";
               suppress = "0";
            }
            SIGNAL s
            {
               name = "zs_dq";
               radix = "hexadecimal";
               suppress = "0";
            }
            SIGNAL t