niso2_1c6.ptf.bak

这个是华清远见 高级班 培训的 实验 代码

            PORT av_writedata
            {
               type = "writedata";
               direction = "input";
               width = "32";
               Is_Enabled = "1";
            }
            PORT av_waitrequest
            {
               type = "waitrequest";
               direction = "output";
               width = "1";
               Is_Enabled = "1";
            }
            PORT av_irq
            {
               type = "irq";
               direction = "output";
               width = "1";
               Is_Enabled = "1";
            }
            PORT dataavailable
            {
               Is_Enabled = "1";
               direction = "output";
               type = "dataavailable";
               width = "1";
            }
            PORT readyfordata
            {
               Is_Enabled = "1";
               direction = "output";
               type = "readyfordata";
               width = "1";
            }
         }
      }
      SYSTEM_BUILDER_INFO 
      {
         Instantiate_In_System_Module = "1";
         Is_Enabled = "1";
         Iss_Launch_Telnet = "0";
         Top_Level_Ports_Are_Enumerated = "1";
         Clock_Source = "clk";
         View 
         {
            Settings_Summary = "<br>Write Depth: 64; Write IRQ Threshold: 8
                <br>Read  Depth: 64; Read  IRQ Threshold: 8";
            MESSAGES 
            {
            }
            Is_Collapsed = "1";
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         write_depth = "64";
         read_depth = "64";
         write_threshold = "8";
         read_threshold = "8";
         read_char_stream = "";
         showascii = "1";
         read_le = "0";
         write_le = "0";
      }
      SIMULATION 
      {
         Fix_Me_Up = "";
         DISPLAY 
         {
            SIGNAL av_chipselect
            {
               name = "av_chipselect";
            }
            SIGNAL av_address
            {
               name = "av_address";
               radix = "hexadecimal";
            }
            SIGNAL av_read_n
            {
               name = "av_read_n";
            }
            SIGNAL av_readdata
            {
               name = "av_readdata";
               radix = "hexadecimal";
            }
            SIGNAL av_write_n
            {
               name = "av_write_n";
            }
            SIGNAL av_writedata
            {
               name = "av_writedata";
               radix = "hexadecimal";
            }
            SIGNAL av_waitrequest
            {
               name = "av_waitrequest";
            }
            SIGNAL av_irq
            {
               name = "av_irq";
            }
            SIGNAL dataavailable
            {
               name = "dataavailable";
            }
            SIGNAL readyfordata
            {
               name = "readyfordata";
            }
         }
         INTERACTIVE_IN drive
         {
            enable = "0";
            file = "_input_data_stream.dat";
            mutex = "_input_data_mutex.dat";
            log = "_in.log";
            rate = "100";
            signals = "temp,list";
            exe = "nios2-terminal";
         }
         INTERACTIVE_OUT log
         {
            enable = "1";
            exe = "perl -- atail-f.pl";
            file = "_output_stream.dat";
            radix = "ascii";
            signals = "temp,list";
         }
      }
      HDL_INFO 
      {
         Precompiled_Simulation_Library_Files = "";
         Simulation_HDL_Files = "";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/jtag_uart.v";
         Synthesis_Only_Files = "";
      }
      PORT_WIRING 
      {
      }
   }
   MODULE spi
   {
      class = "altera_avalon_spi";
      class_version = "2.1";
      SLAVE spi_control_port
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Is_Printable_Device = "0";
            Address_Alignment = "native";
            Address_Width = "3";
            Data_Width = "16";
            Has_IRQ = "1";
            Read_Wait_States = "1";
            Write_Wait_States = "1";
            MASTERED_BY cpu/data_master
            {
               priority = "1";
            }
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "1";
            }
            Base_Address = "0x00200800";
         }
         PORT_WIRING 
         {
            PORT clk
            {
               Is_Enabled = "1";
               direction = "input";
               type = "clk";
               width = "1";
            }
            PORT data_from_cpu
            {
               Is_Enabled = "1";
               direction = "input";
               type = "writedata";
               width = "16";
            }
            PORT data_to_cpu
            {
               Is_Enabled = "1";
               direction = "output";
               type = "readdata";
               width = "16";
            }
            PORT dataavailable
            {
               Is_Enabled = "1";
               direction = "output";
               type = "dataavailable";
               width = "1";
            }
            PORT endofpacket
            {
               Is_Enabled = "1";
               direction = "output";
               type = "endofpacket";
               width = "1";
            }
            PORT irq
            {
               Is_Enabled = "1";
               direction = "output";
               type = "irq";
               width = "1";
            }
            PORT mem_addr
            {
               Is_Enabled = "1";
               direction = "input";
               type = "address";
               width = "3";
            }
            PORT read_n
            {
               Is_Enabled = "1";
               direction = "input";
               type = "read_n";
               width = "1";
            }
            PORT readyfordata
            {
               Is_Enabled = "1";
               direction = "output";
               type = "readyfordata";
               width = "1";
            }
            PORT reset_n
            {
               Is_Enabled = "1";
               direction = "input";
               type = "reset_n";
               width = "1";
            }
            PORT spi_select
            {
               Is_Enabled = "1";
               direction = "input";
               type = "chipselect";
               width = "1";
            }
            PORT write_n
            {
               Is_Enabled = "1";
               direction = "input";
               type = "write_n";
               width = "1";
            }
         }
      }
      SYSTEM_BUILDER_INFO 
      {
         Is_Enabled = "1";
         Instantiate_In_System_Module = "1";
         Top_Level_Ports_Are_Enumerated = "1";
         Clock_Source = "clk";
         View 
         {
            MESSAGES 
            {
            }
            Is_Collapsed = "1";
         }
      }
      PORT_WIRING 
      {
         PORT MISO
         {
            direction = "input";
            width = "1";
            Is_Enabled = "1";
         }
         PORT MOSI
         {
            direction = "output";
            width = "1";
            Is_Enabled = "1";
         }
         PORT SCLK
         {
            direction = "output";
            width = "1";
            Is_Enabled = "1";
         }
         PORT SS_n
         {
            direction = "output";
            width = "1";
            Is_Enabled = "1";
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         databits = "8";
         targetclock = "400";
         clockunits = "kHz";
         clockmult = "1000";
         numslaves = "1";
         ismaster = "1";
         clockpolarity = "1";
         clockphase = "1";
         lsbfirst = "0";
         extradelay = "0";
         targetssdelay = "100";
         delayunits = "us";
         delaymult = "1e-006";
         clockunit = "kHz";
         delayunit = "us";
         prefix = "spi_";
      }
      HDL_INFO 
      {
         Precompiled_Simulation_Library_Files = "";
         Simulation_HDL_Files = "";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/spi.v";
         Synthesis_Only_Files = "";
      }
   }
   MODULE uart
   {
      class = "altera_avalon_uart";
      class_version = "4.2";
      iss_model_name = "altera_avalon_uart";
      PORT_WIRING 
      {
         PORT rxd
         {
            direction = "input";
            width = "1";
            Is_Enabled = "1";
         }
         PORT txd
         {
            direction = "output";
            width = "1";
            Is_Enabled = "1";
         }
         PORT cts_n
         {
            direction = "input";
            width = "1";
            Is_Enabled = "0";
         }
         PORT rts_n
         {
            direction = "output";
            width = "1";
            Is_Enabled = "0";
         }
      }
      SLAVE s1
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Is_Printable_Device = "1";
            Address_Alignment = "native";
            Address_Width = "3";
            Data_Width = "16";
            Has_IRQ = "1";
            Read_Wait_States = "1";
            Write_Wait_States = "1";
            MASTERED_BY cpu/data_master
            {
               priority = "1";
            }
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "2";
            }
            Base_Address = "0x00200820";
         }
         PORT_WIRING 
         {
            PORT address
            {
               Is_Enabled = "1";
               direction = "input";
               type = "address";
               width = "3";
            }
            PORT begintransfer
            {
               Is_Enabled = "1";
               direction = "input";
               type = "begintransfer";
               width = "1";
            }
            PORT chipselect
            {
               Is_Enabled = "1";
               direction = "input";
               type = "chipselect";
               width = "1";
            }
            PORT clk
            {
               Is_Enabled = "1";
               direction = "input";
               type = "clk";
               width = "1";
            }
            PORT dataavailable
            {
               Is_Enabled = "1";
               direction = "output";
               type = "dataavailable";
               width = "1";
            }
            PORT irq
            {
               Is_Enabled = "1";
               direction = "output";
               type = "irq";
               width = "1";
            }
            PORT read_n
            {
               Is_Enabled = "1";
               direction = "input";
               type = "read_n";
               width = "1";
            }
            PORT readdata
            {
               Is_Enabled = "1";
               direction = "output";
               type = "readdata";
               width = "16";
            }
            PORT readyfordata
            {
               Is_Enabled = "1";
               direction = "output";
               type = "readyfordata";
               width = "1";
            }
            PORT reset_n
            {
               Is_Enabled = "1";
               direction = "input";
               type = "reset_n";
               width = "1";
            }
            PORT write_n
            {
               Is_Enabled = "1";
               direction = "input";
               type = "write_n";
               width = "1";