📄 niso2_1c6.ptf.bak
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name = "common";
radix = "";
}
SIGNAL aan
{
format = "Logic";
name = "clk";
radix = "hexadecimal";
}
SIGNAL aao
{
format = "Logic";
name = "reset_n";
radix = "hexadecimal";
}
SIGNAL aap
{
format = "Logic";
name = "F_pcb_nxt";
radix = "hexadecimal";
}
SIGNAL aaq
{
format = "Logic";
name = "F_pcb";
radix = "hexadecimal";
}
SIGNAL aar
{
format = "Logic";
name = "F_vinst";
radix = "ascii";
}
SIGNAL aas
{
format = "Logic";
name = "D_vinst";
radix = "ascii";
}
SIGNAL aat
{
format = "Logic";
name = "R_vinst";
radix = "ascii";
}
SIGNAL aau
{
format = "Logic";
name = "E_vinst";
radix = "ascii";
}
SIGNAL aav
{
format = "Logic";
name = "W_vinst";
radix = "ascii";
}
SIGNAL aaw
{
format = "Logic";
name = "F_valid";
radix = "hexadecimal";
}
SIGNAL aax
{
format = "Logic";
name = "D_valid";
radix = "hexadecimal";
}
SIGNAL aay
{
format = "Logic";
name = "R_valid";
radix = "hexadecimal";
}
SIGNAL aaz
{
format = "Logic";
name = "E_valid";
radix = "hexadecimal";
}
SIGNAL aba
{
format = "Logic";
name = "W_valid";
radix = "hexadecimal";
}
SIGNAL abb
{
format = "Logic";
name = "D_wr_dst_reg";
radix = "hexadecimal";
}
SIGNAL abc
{
format = "Logic";
name = "D_dst_regnum";
radix = "hexadecimal";
}
SIGNAL abd
{
format = "Logic";
name = "W_wr_data";
radix = "hexadecimal";
}
SIGNAL abe
{
format = "Logic";
name = "F_iw";
radix = "hexadecimal";
}
SIGNAL abf
{
format = "Logic";
name = "D_iw";
radix = "hexadecimal";
}
SIGNAL abg
{
format = "Divider";
name = "breaks";
radix = "";
}
SIGNAL abh
{
format = "Logic";
name = "hbreak_req";
radix = "hexadecimal";
}
SIGNAL abi
{
format = "Logic";
name = "oci_hbreak_req";
radix = "hexadecimal";
}
SIGNAL abj
{
format = "Logic";
name = "hbreak_enabled";
radix = "hexadecimal";
}
SIGNAL abk
{
format = "Logic";
name = "wait_for_one_post_bret_inst";
radix = "hexadecimal";
}
}
}
}
MODULE ext_bus
{
class = "altera_avalon_tri_state_bridge";
class_version = "2.0";
SLAVE avalon_slave
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Bridges_To = "tristate_master";
Base_Address = "N/A";
Has_IRQ = "0";
IRQ = "N/A";
Register_Outgoing_Signals = "1";
Register_Incoming_Signals = "1";
MASTERED_BY cpu/instruction_master
{
priority = "1";
}
MASTERED_BY cpu/data_master
{
priority = "1";
}
IRQ_MASTER cpu/data_master
{
IRQ_Number = "NC";
}
}
}
MASTER tristate_master
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon_tristate";
Bridges_To = "avalon_slave";
}
}
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "1";
Is_Enabled = "1";
Is_Bridge = "1";
Top_Level_Ports_Are_Enumerated = "1";
Clock_Source = "clk";
View
{
MESSAGES
{
}
Is_Collapsed = "1";
}
}
}
MODULE ext_flash
{
class = "altera_avalon_cfi_flash";
class_version = "1.1";
iss_model_name = "altera_avalon_flash";
HDL_INFO
{
}
SLAVE s1
{
PORT_WIRING
{
PORT data
{
width = "16";
is_shared = "1";
direction = "inout";
type = "data";
}
PORT address
{
width = "20";
is_shared = "1";
direction = "input";
type = "address";
}
PORT read_n
{
width = "1";
is_shared = "1";
direction = "input";
type = "read_n";
}
PORT write_n
{
width = "1";
is_shared = "1";
direction = "input";
type = "write_n";
}
PORT select_n
{
width = "1";
is_shared = "0";
direction = "input";
type = "chipselect_n";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
class = "altera_avalon_cfi_flash";
Supports_Flash_File_System = "1";
flash_reference_designator = "U7";
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon_tristate";
Is_Nonvolatile_Storage = "1";
Is_Memory_Device = "1";
Address_Alignment = "dynamic";
Has_IRQ = "0";
Base_Address = "0x00000000";
Data_Width = "16";
Address_Width = "20";
Simulation_Num_Lanes = "2";
Convert_Xs_To_0 = "1";
Write_Wait_States = "160ns";
Read_Wait_States = "160ns";
Setup_Time = "40ns";
Hold_Time = "40ns";
Address_Span = "2097152";
MASTERED_BY ext_bus/tristate_master
{
priority = "1";
}
IRQ_MASTER cpu/data_master
{
IRQ_Number = "NC";
}
}
}
SYSTEM_BUILDER_INFO
{
Make_Memory_Model = "1";
Is_Enabled = "1";
Instantiate_In_System_Module = "0";
Top_Level_Ports_Are_Enumerated = "1";
Clock_Source = "clk";
View
{
MESSAGES
{
}
Is_Collapsed = "1";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
Setup_Value = "40";
Wait_Value = "160";
Hold_Value = "40";
Timing_Units = "ns";
Unit_Multiplier = "1";
Size = "2097152";
MAKE
{
MACRO
{
EXT_FLASH_FLASHTARGET_ALT_SIM_PREFIX = "$(EXT_FLASH_FLASHTARGET_TMP1:0=)";
EXT_FLASH_FLASHTARGET_TMP1 = "$(ALT_SIM_OPTIMIZE:1=RUN_ON_HDL_SIMULATOR_ONLY_)";
}
MASTER cpu
{
MACRO
{
BOOT_COPIER = "boot_loader_cfi.srec";
CPU_CLASS = "altera_nios2";
CPU_RESET_ADDRESS = "0x0";
}
}
TARGET delete_placeholder_warning
{
ext_flash
{
Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt";
Is_Phony = "1";
Target_File = "do_delete_placeholder_warning";
}
}
TARGET flashfiles
{
ext_flash
{
Command1 = "@echo Post-processing to create $(notdir $@)";
Command2 = "elf2flash --input=$(ELF) --flash=U7 --boot=$(shell $(QUARTUS_ROOTDIR)/sopc_builder/bin/find_sopc_component_dir $(CPU_CLASS))/$(BOOT_COPIER) --outfile=$(EXT_FLASH_FLASHTARGET_ALT_SIM_PREFIX)ext_flash.flash --sim_optimize=$(ALT_SIM_OPTIMIZE) --base=0x0 --end=0x1FFFFF --reset=$(CPU_RESET_ADDRESS) ";
Dependency = "$(ELF)";
Target_File = "$(EXT_FLASH_FLASHTARGET_ALT_SIM_PREFIX)ext_flash.flash";
}
}
TARGET programflash
{
ext_flash
{
All_Depends_On = "0";
Command1 = "nios2-flash-programmer --input=$(EXT_FLASH_FLASHTARGET_ALT_SIM_PREFIX)ext_flash.flash --sof=$(shell $(QUARTUS_ROOTDIR)/sopc_builder/bin/find_sopc_component_dir SmartSOPC_Board_1C6)/system/SmartSOPC_Board_Cyclone_1C6.sof --device=1 $(JTAG_CABLE) --base=0x00200000 ";
Dependency = "$(EXT_FLASH_FLASHTARGET_ALT_SIM_PREFIX)ext_flash.flash";
Is_Phony = "1";
Target_File = "ext_flash_programflash";
}
}
TARGET programflashnoelfdependency
{
ext_flash
{
All_Depends_On = "0";
Command1 = "nios2-flash-programmer --input=$(EXT_FLASH_FLASHTARGET_ALT_SIM_PREFIX)ext_flash.flash --sof=$(shell $(QUARTUS_ROOTDIR)/sopc_builder/bin/find_sopc_component_dir SmartSOPC_Board_1C6)/system/SmartSOPC_Board_Cyclone_1C6.sof --device=1 $(JTAG_CABLE) --base=0x00200000 ";
Is_Phony = "1";
Target_File = "ext_flash_programflashnoelf";
}
}
TARGET sim
{
ext_flash
{
Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";
Command2 = "@echo Hardware simulation is not enabled for the target SOPC Builder system. Skipping creation of hardware simulation model contents and simulation symbol files. \\(Note: This does not affect the instruction set simulator.\\)";
Command3 = "touch $(SIMDIR)/dummy_file";
Dependency = "$(ELF)";
Target_File = "$(SIMDIR)/dummy_file";
}
}
}
}
}
MODULE jtag_uart
{
class = "altera_avalon_jtag_uart";
class_version = "1.0";
iss_model_name = "altera_avalon_jtag_uart";
SLAVE avalon_jtag_slave
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Is_Printable_Device = "1";
Address_Alignment = "native";
Address_Width = "1";
Data_Width = "32";
Has_IRQ = "1";
Read_Wait_States = "peripheral_controlled";
Write_Wait_States = "peripheral_controlled";
JTAG_Hub_Base_Id = "0x04006E";
JTAG_Hub_Instance_Id = "0";
Connection_Limit = "1";
MASTERED_BY cpu/data_master
{
priority = "1";
}
IRQ_MASTER cpu/data_master
{
IRQ_Number = "0";
}
Base_Address = "0x002008A0";
}
PORT_WIRING
{
PORT clk
{
type = "clk";
direction = "input";
width = "1";
Is_Enabled = "1";
}
PORT rst_n
{
type = "reset_n";
direction = "input";
width = "1";
Is_Enabled = "1";
}
PORT av_chipselect
{
type = "chipselect";
direction = "input";
width = "1";
Is_Enabled = "1";
}
PORT av_address
{
type = "address";
direction = "input";
width = "1";
Is_Enabled = "1";
}
PORT av_read_n
{
type = "read_n";
direction = "input";
width = "1";
Is_Enabled = "1";
}
PORT av_readdata
{
type = "readdata";
direction = "output";
width = "32";
Is_Enabled = "1";
}
PORT av_write_n
{
type = "write_n";
direction = "input";
width = "1";
Is_Enabled = "1";
}
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