testusb.tan.qmsg

fpga之ep1 c6的usb实验源码,经实验验证好好用,大家可以试试看哦

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Oct 24 19:40:18 2007 " "Info: Processing started: Wed Oct 24 19:40:18 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off TestUSB -c TestUSB --timing_analysis_only " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off TestUSB -c TestUSB --timing_analysis_only" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "USB_DS_ " "Info: Assuming node \"USB_DS_\" is an undefined clock" {  } { { "testusb.v" "" { Text "G:/ezNiosC6C/TestUSB/testusb.v" 8 -1 0 } } { "c:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "USB_DS_" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "USB_WR_ " "Info: Assuming node \"USB_WR_\" is an undefined clock" {  } { { "testusb.v" "" { Text "G:/ezNiosC6C/TestUSB/testusb.v" 8 -1 0 } } { "c:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "USB_WR_" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "USB_AS_ " "Info: Assuming node \"USB_AS_\" is an undefined clock" {  } { { "testusb.v" "" { Text "G:/ezNiosC6C/TestUSB/testusb.v" 8 -1 0 } } { "c:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "USB_AS_" } } } }  } 0}  } {  } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "clk_usbwra " "Info: Detected gated clock \"clk_usbwra\" as buffer" {  } { { "testusb.v" "" { Text "G:/ezNiosC6C/TestUSB/testusb.v" 26 -1 0 } } { "c:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "clk_usbwra" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "clk_usbwrd " "Info: Detected gated clock \"clk_usbwrd\" as buffer" {  } { { "testusb.v" "" { Text "G:/ezNiosC6C/TestUSB/testusb.v" 42 -1 0 } } { "c:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "clk_usbwrd" } } } }  } 0}  } {  } 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "USB_DS_ " "Info: No valid register-to-register data paths exist for clock \"USB_DS_\"" {  } {  } 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "USB_WR_ " "Info: No valid register-to-register data paths exist for clock \"USB_WR_\"" {  } {  } 0}