testusb.fit.qmsg

fpga之ep1 c6的usb实验源码,经实验验证好好用,大家可以试试看哦

{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk_usbwra Global clock " "Info: Automatically promoted signal \"clk_usbwra\" to use Global clock" {  } { { "testusb.v" "" { Text "G:/ezNiosC6C/TestUSB/testusb.v" 26 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk_usbwrd Global clock " "Info: Automatically promoted signal \"clk_usbwrd\" to use Global clock" {  } { { "testusb.v" "" { Text "G:/ezNiosC6C/TestUSB/testusb.v" 42 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "RESET_ Global clock " "Info: Automatically promoted signal \"RESET_\" to use Global clock" {  } { { "testusb.v" "" { Text "G:/ezNiosC6C/TestUSB/testusb.v" 6 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "RESET_ " "Info: Pin \"RESET_\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "testusb.v" "" { Text "G:/ezNiosC6C/TestUSB/testusb.v" 6 -1 0 } } { "c:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "RESET_" } } } } { "G:/ezNiosC6C/TestUSB/db/TestUSB_cmp.qrpt" "" { Report "G:/ezNiosC6C/TestUSB/db/TestUSB_cmp.qrpt" Compiler "TestUSB" "UNKNOWN" "V1" "G:/ezNiosC6C/TestUSB/db/TestUSB.quartus_db" { Floorplan "G:/ezNiosC6C/TestUSB/" "" "" { RESET_ } "NODE_NAME" } "" } } { "G:/ezNiosC6C/TestUSB/TestUSB.fld" "" { Floorplan "G:/ezNiosC6C/TestUSB/TestUSB.fld" "" "" { RESET_ } "NODE_NAME" } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0}