testusb.map.qmsg

fpga之ep1 c6的usb实验源码,经实验验证好好用,大家可以试试看哦

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Oct 24 19:39:56 2007 " "Info: Processing started: Wed Oct 24 19:39:56 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off TestUSB -c TestUSB " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off TestUSB -c TestUSB" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "testusb.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file testusb.v" { { "Info" "ISGN_ENTITY_NAME" "1 TestUSB " "Info: Found entity 1: TestUSB" {  } { { "testusb.v" "" { Text "G:/ezNiosC6C/TestUSB/testusb.v" 3 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "USB_INT_ VCC " "Warning: Pin \"USB_INT_\" stuck at VCC" {  } { { "testusb.v" "" { Text "G:/ezNiosC6C/TestUSB/testusb.v" 7 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "SDRAM_CS_ VCC " "Warning: Pin \"SDRAM_CS_\" stuck at VCC" {  } { { "testusb.v" "" { Text "G:/ezNiosC6C/TestUSB/testusb.v" 12 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "FLASH_CE_ VCC " "Warning: Pin \"FLASH_CE_\" stuck at VCC" {  } { { "testusb.v" "" { Text "G:/ezNiosC6C/TestUSB/testusb.v" 13 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "48 " "Info: Implemented 48 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "4 " "Info: Implemented 4 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "7 " "Info: Implemented 7 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_BIDIRS" "8 " "Info: Implemented 8 bidirectional pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "29 " "Info: Implemented 29 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Oct 24 19:39:58 2007 " "Info: Processing ended: Wed Oct 24 19:39:58 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}