📄 testusb.tan.rpt
字号:
; N/A ; None ; 13.006 ns ; DataReg[4] ; USB_D[4] ; USB_WR_ ;
; N/A ; None ; 12.909 ns ; DataReg[0] ; USB_D[0] ; USB_DS_ ;
; N/A ; None ; 12.904 ns ; DataReg[1] ; USB_D[1] ; USB_DS_ ;
; N/A ; None ; 12.903 ns ; AddrReg[0] ; USB_D[0] ; USB_WR_ ;
; N/A ; None ; 12.853 ns ; DataReg[2] ; USB_D[2] ; USB_WR_ ;
; N/A ; None ; 12.820 ns ; DataReg[3] ; USB_D[3] ; USB_DS_ ;
; N/A ; None ; 12.758 ns ; DataReg[4] ; USB_D[4] ; USB_DS_ ;
; N/A ; None ; 12.690 ns ; AddrReg[0] ; USB_D[0] ; USB_AS_ ;
; N/A ; None ; 12.605 ns ; DataReg[2] ; USB_D[2] ; USB_DS_ ;
; N/A ; None ; 12.594 ns ; AddrReg[3] ; USB_D[3] ; USB_WR_ ;
; N/A ; None ; 12.593 ns ; AddrReg[2] ; USB_D[2] ; USB_WR_ ;
; N/A ; None ; 12.586 ns ; AddrReg[1] ; USB_D[1] ; USB_WR_ ;
; N/A ; None ; 12.442 ns ; AddrReg[4] ; USB_D[4] ; USB_WR_ ;
; N/A ; None ; 12.381 ns ; AddrReg[3] ; USB_D[3] ; USB_AS_ ;
; N/A ; None ; 12.380 ns ; AddrReg[2] ; USB_D[2] ; USB_AS_ ;
; N/A ; None ; 12.373 ns ; AddrReg[1] ; USB_D[1] ; USB_AS_ ;
; N/A ; None ; 12.229 ns ; AddrReg[4] ; USB_D[4] ; USB_AS_ ;
+-------+--------------+------------+------------+----------+------------+
+------------------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+---------+----------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+---------+----------+
; N/A ; None ; 13.686 ns ; USB_WR_ ; USB_D[0] ;
; N/A ; None ; 13.414 ns ; USB_AS_ ; USB_D[0] ;
; N/A ; None ; 13.375 ns ; USB_WR_ ; USB_D[2] ;
; N/A ; None ; 13.373 ns ; USB_WR_ ; USB_D[3] ;
; N/A ; None ; 13.362 ns ; USB_WR_ ; USB_D[1] ;
; N/A ; None ; 13.224 ns ; USB_WR_ ; USB_D[4] ;
; N/A ; None ; 13.215 ns ; USB_DS_ ; USB_D[0] ;
; N/A ; None ; 13.121 ns ; USB_WR_ ; USB_D[6] ;
; N/A ; None ; 13.103 ns ; USB_AS_ ; USB_D[2] ;
; N/A ; None ; 13.101 ns ; USB_AS_ ; USB_D[3] ;
; N/A ; None ; 13.090 ns ; USB_WR_ ; USB_D[5] ;
; N/A ; None ; 13.090 ns ; USB_AS_ ; USB_D[1] ;
; N/A ; None ; 12.952 ns ; USB_AS_ ; USB_D[4] ;
; N/A ; None ; 12.906 ns ; USB_DS_ ; USB_D[2] ;
; N/A ; None ; 12.904 ns ; USB_DS_ ; USB_D[3] ;
; N/A ; None ; 12.842 ns ; USB_DS_ ; USB_D[6] ;
; N/A ; None ; 12.811 ns ; USB_DS_ ; USB_D[5] ;
; N/A ; None ; 12.648 ns ; USB_WR_ ; USB_D[7] ;
; N/A ; None ; 12.577 ns ; USB_DS_ ; USB_D[1] ;
; N/A ; None ; 12.439 ns ; USB_DS_ ; USB_D[4] ;
; N/A ; None ; 12.413 ns ; USB_AS_ ; USB_D[6] ;
; N/A ; None ; 12.382 ns ; USB_AS_ ; USB_D[5] ;
; N/A ; None ; 12.376 ns ; USB_AS_ ; USB_D[7] ;
; N/A ; None ; 12.028 ns ; USB_DS_ ; USB_D[7] ;
+-------+-------------------+-----------------+---------+----------+
+----------------------------------------------------------------------------+
; th ;
+---------------+-------------+-----------+----------+------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;
+---------------+-------------+-----------+----------+------------+----------+
; N/A ; None ; 2.450 ns ; USB_D[4] ; DataReg[4] ; USB_WR_ ;
; N/A ; None ; 2.447 ns ; USB_D[4] ; AddrReg[4] ; USB_WR_ ;
; N/A ; None ; 2.234 ns ; USB_D[4] ; AddrReg[4] ; USB_AS_ ;
; N/A ; None ; 2.202 ns ; USB_D[4] ; DataReg[4] ; USB_DS_ ;
; N/A ; None ; 2.005 ns ; USB_D[2] ; DataReg[2] ; USB_WR_ ;
; N/A ; None ; 2.004 ns ; USB_D[2] ; AddrReg[2] ; USB_WR_ ;
; N/A ; None ; 1.989 ns ; USB_D[1] ; DataReg[1] ; USB_WR_ ;
; N/A ; None ; 1.988 ns ; USB_D[1] ; AddrReg[1] ; USB_WR_ ;
; N/A ; None ; 1.937 ns ; USB_D[3] ; DataReg[3] ; USB_WR_ ;
; N/A ; None ; 1.937 ns ; USB_D[3] ; AddrReg[3] ; USB_WR_ ;
; N/A ; None ; 1.791 ns ; USB_D[2] ; AddrReg[2] ; USB_AS_ ;
; N/A ; None ; 1.775 ns ; USB_D[1] ; AddrReg[1] ; USB_AS_ ;
; N/A ; None ; 1.757 ns ; USB_D[2] ; DataReg[2] ; USB_DS_ ;
; N/A ; None ; 1.741 ns ; USB_D[1] ; DataReg[1] ; USB_DS_ ;
; N/A ; None ; 1.724 ns ; USB_D[3] ; AddrReg[3] ; USB_AS_ ;
; N/A ; None ; 1.711 ns ; USB_D[0] ; DataReg[0] ; USB_WR_ ;
; N/A ; None ; 1.704 ns ; USB_D[0] ; AddrReg[0] ; USB_WR_ ;
; N/A ; None ; 1.689 ns ; USB_D[3] ; DataReg[3] ; USB_DS_ ;
; N/A ; None ; 1.491 ns ; USB_D[0] ; AddrReg[0] ; USB_AS_ ;
; N/A ; None ; 1.463 ns ; USB_D[0] ; DataReg[0] ; USB_DS_ ;
; N/A ; None ; 1.247 ns ; USB_D[7] ; AddrReg[7] ; USB_WR_ ;
; N/A ; None ; 1.246 ns ; USB_D[7] ; DataReg[7] ; USB_WR_ ;
; N/A ; None ; 1.186 ns ; USB_D[5] ; AddrReg[5] ; USB_WR_ ;
; N/A ; None ; 1.185 ns ; USB_D[6] ; AddrReg[6] ; USB_WR_ ;
; N/A ; None ; 1.183 ns ; USB_D[6] ; DataReg[6] ; USB_WR_ ;
; N/A ; None ; 1.036 ns ; USB_D[5] ; DataReg[5] ; USB_WR_ ;
; N/A ; None ; 1.034 ns ; USB_D[7] ; AddrReg[7] ; USB_AS_ ;
; N/A ; None ; 0.998 ns ; USB_D[7] ; DataReg[7] ; USB_DS_ ;
; N/A ; None ; 0.973 ns ; USB_D[5] ; AddrReg[5] ; USB_AS_ ;
; N/A ; None ; 0.972 ns ; USB_D[6] ; AddrReg[6] ; USB_AS_ ;
; N/A ; None ; 0.935 ns ; USB_D[6] ; DataReg[6] ; USB_DS_ ;
; N/A ; None ; 0.788 ns ; USB_D[5] ; DataReg[5] ; USB_DS_ ;
+---------------+-------------+-----------+----------+------------+----------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
Info: Processing started: Wed Oct 24 19:40:18 2007
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off TestUSB -c TestUSB --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "USB_DS_" is an undefined clock
Info: Assuming node "USB_WR_" is an undefined clock
Info: Assuming node "USB_AS_" is an undefined clock
Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
Info: Detected gated clock "clk_usbwra" as buffer
Info: Detected gated clock "clk_usbwrd" as buffer
Info: No valid register-to-register data paths exist for clock "USB_DS_"
Info: No valid register-to-register data paths exist for clock "USB_WR_"
Info: No valid register-to-register data paths exist for clock "USB_AS_"
Info: tsu for register "DataReg[5]" (data pin = "USB_D[5]", clock pin = "USB_DS_") is -0.736 ns
Info: + Longest pin to register delay is 7.611 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_179; Fanout = 1; PIN Node = 'USB_D[5]'
Info: 2: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = IOC_X35_Y20_N1; Fanout = 2; COMB Node = 'USB_D[5]~2'
Info: 3: + IC(5.833 ns) + CELL(0.309 ns) = 7.611 ns; Loc. = LC_X33_Y14_N9; Fanout = 1; REG Node = 'DataReg[5]'
Info: Total cell delay = 1.778 ns ( 23.36 % )
Info: Total interconnect delay = 5.833 ns ( 76.64 % )
Info: + Micro setup delay of destination is 0.037 ns
Info: - Shortest clock path from clock "USB_DS_" to destination register is 8.384 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_163; Fanout = 3; CLK Node = 'USB_DS_'
Info: 2: + IC(1.587 ns) + CELL(0.292 ns) = 3.348 ns; Loc. = LC_X32_Y14_N9; Fanout = 8; COMB Node = 'clk_usbwrd'
Info: 3: + IC(4.325 ns) + CELL(0.711 ns) = 8.384 ns; Loc. = LC_X33_Y14_N9; Fanout = 1; REG Node = 'DataReg[5]'
Info: Total cell delay = 2.472 ns ( 29.48 % )
Info: Total interconnect delay = 5.912 ns ( 70.52 % )
Info: tco from clock "USB_WR_" to destination pin "LED[0]" through register "DataReg[0]" is 14.646 ns
Info: + Longest clock path from clock "USB_WR_" to source register is 8.632 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_176; Fanout = 5; CLK Node = 'USB_WR_'
Info: 2: + IC(2.013 ns) + CELL(0.114 ns) = 3.596 ns; Loc. = LC_X32_Y14_N9; Fanout = 8; COMB Node = 'clk_usbwrd'
Info: 3: + IC(4.325 ns) + CELL(0.711 ns) = 8.632 ns; Loc. = LC_X34_Y20_N1; Fanout = 2; REG Node = 'DataReg[0]'
Info: Total cell delay = 2.294 ns ( 26.58 % )
Info: Total interconnect delay = 6.338 ns ( 73.42 % )
Info: + Micro clock to output delay of source is 0.224 ns
Info: + Longest register to pin delay is 5.790 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X34_Y20_N1; Fanout = 2; REG Node = 'DataReg[0]'
Info: 2: + IC(3.682 ns) + CELL(2.108 ns) = 5.790 ns; Loc. = PIN_117; Fanout = 0; PIN Node = 'LED[0]'
Info: Total cell delay = 2.108 ns ( 36.41 % )
Info: Total interconnect delay = 3.682 ns ( 63.59 % )
Info: Longest tpd from source pin "USB_WR_" to destination pin "USB_D[0]" is 13.686 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_176; Fanout = 5; CLK Node = 'USB_WR_'
Info: 2: + IC(5.849 ns) + CELL(0.114 ns) = 7.432 ns; Loc. = LC_X32_Y14_N4; Fanout = 8; COMB Node = 'put_addrreg'
Info: 3: + IC(1.994 ns) + CELL(0.590 ns) = 10.016 ns; Loc. = LC_X34_Y20_N6; Fanout = 1; COMB Node = 'USB_D[0]~502'
Info: 4: + IC(1.562 ns) + CELL(2.108 ns) = 13.686 ns; Loc. = PIN_184; Fanout = 0; PIN Node = 'USB_D[0]'
Info: Total cell delay = 4.281 ns ( 31.28 % )
Info: Total interconnect delay = 9.405 ns ( 68.72 % )
Info: th for register "DataReg[4]" (data pin = "USB_D[4]", clock pin = "USB_WR_") is 2.450 ns
Info: + Longest clock path from clock "USB_WR_" to destination register is 8.632 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_176; Fanout = 5; CLK Node = 'USB_WR_'
Info: 2: + IC(2.013 ns) + CELL(0.114 ns) = 3.596 ns; Loc. = LC_X32_Y14_N9; Fanout = 8; COMB Node = 'clk_usbwrd'
Info: 3: + IC(4.325 ns) + CELL(0.711 ns) = 8.632 ns; Loc. = LC_X34_Y20_N4; Fanout = 1; REG Node = 'DataReg[4]'
Info: Total cell delay = 2.294 ns ( 26.58 % )
Info: Total interconnect delay = 6.338 ns ( 73.42 % )
Info: + Micro hold delay of destination is 0.015 ns
Info: - Shortest pin to register delay is 6.197 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_180; Fanout = 1; PIN Node = 'USB_D[4]'
Info: 2: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = IOC_X35_Y20_N0; Fanout = 2; COMB Node = 'USB_D[4]~3'
Info: 3: + IC(4.613 ns) + CELL(0.115 ns) = 6.197 ns; Loc. = LC_X34_Y20_N4; Fanout = 1; REG Node = 'DataReg[4]'
Info: Total cell delay = 1.584 ns ( 25.56 % )
Info: Total interconnect delay = 4.613 ns ( 74.44 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
Info: Processing ended: Wed Oct 24 19:40:18 2007
Info: Elapsed time: 00:00:01
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