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📄 testusb.tan.rpt

📁 fpga之ep1 c6的usb实验源码,经实验验证好好用,大家可以试试看哦
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Timing Analyzer report for TestUSB
Wed Oct 24 19:40:18 2007
Version 4.2 Build 157 12/07/2004 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. tsu
  6. tco
  7. tpd
  8. th
  9. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.



+-------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                             ;
+------------------------------+-------+---------------+-------------+------------+------------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time ; From       ; To         ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------------+------------+------------+----------+--------------+
; Worst-case tsu               ; N/A   ; None          ; -0.736 ns   ; USB_D[5]   ; DataReg[5] ;            ; USB_DS_  ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 14.646 ns   ; DataReg[0] ; LED[0]     ; USB_WR_    ;          ; 0            ;
; Worst-case tpd               ; N/A   ; None          ; 13.686 ns   ; USB_WR_    ; USB_D[0]   ;            ;          ; 0            ;
; Worst-case th                ; N/A   ; None          ; 2.450 ns    ; USB_D[4]   ; DataReg[4] ;            ; USB_WR_  ; 0            ;
; Total number of failed paths ;       ;               ;             ;            ;            ;            ;          ; 0            ;
+------------------------------+-------+---------------+-------------+------------+------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C6Q240C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minumum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Clock Analysis Only                                   ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off clear and preset signal paths                 ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Do Min/Max analysis using Rise/Fall delays            ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Use Clock Latency for PLL offset                      ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                               ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; USB_DS_         ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
; USB_WR_         ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
; USB_AS_         ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+


+----------------------------------------------------------------------+
; tsu                                                                  ;
+-------+--------------+------------+----------+------------+----------+
; Slack ; Required tsu ; Actual tsu ; From     ; To         ; To Clock ;
+-------+--------------+------------+----------+------------+----------+
; N/A   ; None         ; -0.736 ns  ; USB_D[5] ; DataReg[5] ; USB_DS_  ;
; N/A   ; None         ; -0.883 ns  ; USB_D[6] ; DataReg[6] ; USB_DS_  ;
; N/A   ; None         ; -0.920 ns  ; USB_D[6] ; AddrReg[6] ; USB_AS_  ;
; N/A   ; None         ; -0.921 ns  ; USB_D[5] ; AddrReg[5] ; USB_AS_  ;
; N/A   ; None         ; -0.946 ns  ; USB_D[7] ; DataReg[7] ; USB_DS_  ;
; N/A   ; None         ; -0.982 ns  ; USB_D[7] ; AddrReg[7] ; USB_AS_  ;
; N/A   ; None         ; -0.984 ns  ; USB_D[5] ; DataReg[5] ; USB_WR_  ;
; N/A   ; None         ; -1.131 ns  ; USB_D[6] ; DataReg[6] ; USB_WR_  ;
; N/A   ; None         ; -1.133 ns  ; USB_D[6] ; AddrReg[6] ; USB_WR_  ;
; N/A   ; None         ; -1.134 ns  ; USB_D[5] ; AddrReg[5] ; USB_WR_  ;
; N/A   ; None         ; -1.194 ns  ; USB_D[7] ; DataReg[7] ; USB_WR_  ;
; N/A   ; None         ; -1.195 ns  ; USB_D[7] ; AddrReg[7] ; USB_WR_  ;
; N/A   ; None         ; -1.411 ns  ; USB_D[0] ; DataReg[0] ; USB_DS_  ;
; N/A   ; None         ; -1.439 ns  ; USB_D[0] ; AddrReg[0] ; USB_AS_  ;
; N/A   ; None         ; -1.637 ns  ; USB_D[3] ; DataReg[3] ; USB_DS_  ;
; N/A   ; None         ; -1.652 ns  ; USB_D[0] ; AddrReg[0] ; USB_WR_  ;
; N/A   ; None         ; -1.659 ns  ; USB_D[0] ; DataReg[0] ; USB_WR_  ;
; N/A   ; None         ; -1.672 ns  ; USB_D[3] ; AddrReg[3] ; USB_AS_  ;
; N/A   ; None         ; -1.689 ns  ; USB_D[1] ; DataReg[1] ; USB_DS_  ;
; N/A   ; None         ; -1.705 ns  ; USB_D[2] ; DataReg[2] ; USB_DS_  ;
; N/A   ; None         ; -1.723 ns  ; USB_D[1] ; AddrReg[1] ; USB_AS_  ;
; N/A   ; None         ; -1.739 ns  ; USB_D[2] ; AddrReg[2] ; USB_AS_  ;
; N/A   ; None         ; -1.885 ns  ; USB_D[3] ; DataReg[3] ; USB_WR_  ;
; N/A   ; None         ; -1.885 ns  ; USB_D[3] ; AddrReg[3] ; USB_WR_  ;
; N/A   ; None         ; -1.936 ns  ; USB_D[1] ; AddrReg[1] ; USB_WR_  ;
; N/A   ; None         ; -1.937 ns  ; USB_D[1] ; DataReg[1] ; USB_WR_  ;
; N/A   ; None         ; -1.952 ns  ; USB_D[2] ; AddrReg[2] ; USB_WR_  ;
; N/A   ; None         ; -1.953 ns  ; USB_D[2] ; DataReg[2] ; USB_WR_  ;
; N/A   ; None         ; -2.150 ns  ; USB_D[4] ; DataReg[4] ; USB_DS_  ;
; N/A   ; None         ; -2.182 ns  ; USB_D[4] ; AddrReg[4] ; USB_AS_  ;
; N/A   ; None         ; -2.395 ns  ; USB_D[4] ; AddrReg[4] ; USB_WR_  ;
; N/A   ; None         ; -2.398 ns  ; USB_D[4] ; DataReg[4] ; USB_WR_  ;
+-------+--------------+------------+----------+------------+----------+


+------------------------------------------------------------------------+
; tco                                                                    ;
+-------+--------------+------------+------------+----------+------------+
; Slack ; Required tco ; Actual tco ; From       ; To       ; From Clock ;
+-------+--------------+------------+------------+----------+------------+
; N/A   ; None         ; 14.646 ns  ; DataReg[0] ; LED[0]   ; USB_WR_    ;
; N/A   ; None         ; 14.411 ns  ; DataReg[2] ; LED[2]   ; USB_WR_    ;
; N/A   ; None         ; 14.398 ns  ; DataReg[0] ; LED[0]   ; USB_DS_    ;
; N/A   ; None         ; 14.307 ns  ; AddrReg[7] ; USB_D[7] ; USB_WR_    ;
; N/A   ; None         ; 14.163 ns  ; DataReg[2] ; LED[2]   ; USB_DS_    ;
; N/A   ; None         ; 14.094 ns  ; AddrReg[7] ; USB_D[7] ; USB_AS_    ;
; N/A   ; None         ; 14.052 ns  ; DataReg[5] ; USB_D[5] ; USB_WR_    ;
; N/A   ; None         ; 13.965 ns  ; DataReg[3] ; LED[3]   ; USB_WR_    ;
; N/A   ; None         ; 13.926 ns  ; DataReg[1] ; LED[1]   ; USB_WR_    ;
; N/A   ; None         ; 13.865 ns  ; DataReg[6] ; USB_D[6] ; USB_WR_    ;
; N/A   ; None         ; 13.804 ns  ; DataReg[5] ; USB_D[5] ; USB_DS_    ;
; N/A   ; None         ; 13.717 ns  ; DataReg[3] ; LED[3]   ; USB_DS_    ;
; N/A   ; None         ; 13.678 ns  ; DataReg[1] ; LED[1]   ; USB_DS_    ;
; N/A   ; None         ; 13.617 ns  ; DataReg[6] ; USB_D[6] ; USB_DS_    ;
; N/A   ; None         ; 13.607 ns  ; AddrReg[6] ; USB_D[6] ; USB_WR_    ;
; N/A   ; None         ; 13.576 ns  ; AddrReg[5] ; USB_D[5] ; USB_WR_    ;
; N/A   ; None         ; 13.572 ns  ; DataReg[7] ; USB_D[7] ; USB_WR_    ;
; N/A   ; None         ; 13.394 ns  ; AddrReg[6] ; USB_D[6] ; USB_AS_    ;
; N/A   ; None         ; 13.363 ns  ; AddrReg[5] ; USB_D[5] ; USB_AS_    ;
; N/A   ; None         ; 13.324 ns  ; DataReg[7] ; USB_D[7] ; USB_DS_    ;
; N/A   ; None         ; 13.157 ns  ; DataReg[0] ; USB_D[0] ; USB_WR_    ;
; N/A   ; None         ; 13.152 ns  ; DataReg[1] ; USB_D[1] ; USB_WR_    ;
; N/A   ; None         ; 13.068 ns  ; DataReg[3] ; USB_D[3] ; USB_WR_    ;

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