testusb.v

来自「fpga之ep1 c6的usb实验源码,经实验验证好好用,大家可以试试看哦」· Verilog 代码 · 共 57 行

`define Tgate 1
`timescale 1ns/10ps
module TestUSB( RESET_,USB_WR_,USB_AS_,USB_DS_,USB_INT_,USB_D,
SDRAM_CS_,FLASH_CE_,LED);

input RESET_;	     
output USB_INT_;
input  USB_WR_,USB_AS_,USB_DS_;

inout[7:0] USB_D;

output	SDRAM_CS_	; 
output	FLASH_CE_	;

output[3:0] LED;
    
assign	SDRAM_CS_ = 1'b1;
assign	FLASH_CE_ = 1'b1; 
assign  USB_INT_ = 1'b1;


wire por = ~RESET_;
/************************************************
访问地址寄存器
************************************************/
wire clk_usbwra = (USB_WR_ | USB_AS_); //generate usb write addr clk
reg[7:0] AddrReg;
always @(posedge clk_usbwra or posedge por)
	if(por==1)	
	  AddrReg <= #`Tgate 0;
	else 
	  AddrReg <= #`Tgate USB_D[7:0];
	
//for:read addrreg
wire put_addrreg = USB_WR_ & (~USB_AS_);
assign USB_D = put_addrreg ? AddrReg : 8'hzz;


/************************************************
访问数据寄存器
************************************************/
wire clk_usbwrd = USB_WR_ | USB_DS_;   //generate usb write data clk
reg[7:0] DataReg;
always @(posedge clk_usbwrd or posedge por)
	if(por==1)	
	  DataReg <= #`Tgate 0;
	else 
	  DataReg <= #`Tgate USB_D[7:0];

//generate data reg read signal
wire put_dreg = USB_WR_ & (~USB_DS_);
//for:read
assign USB_D = (put_dreg) ? DataReg : 8'hzz;

assign LED[3:0] = ~DataReg[3:0];
endmodule