📄 testusb.map.rpt
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Analysis & Synthesis report for TestUSB
Wed Oct 24 19:39:58 2007
Version 4.2 Build 157 12/07/2004 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Hierarchy
5. Analysis & Synthesis Resource Utilization by Entity
6. Analysis & Synthesis Equations
7. Analysis & Synthesis Source Files Read
8. Analysis & Synthesis Resource Usage Summary
9. WYSIWYG Cells
10. General Register Statistics
11. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any megafunction design, and related netlist (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only
to program PLD devices (but not masked PLD devices) from Altera. Any
other use of such megafunction design, netlist, support information,
device programming or simulation file, or any other related documentation
or information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to the
intellectual property, including patents, copyrights, trademarks, trade
secrets, or maskworks, embodied in any such megafunction design, netlist,
support information, device programming or simulation file, or any other
related documentation or information provided by Altera or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.
+------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Wed Oct 24 19:39:58 2007 ;
; Quartus II Version ; 4.2 Build 157 12/07/2004 SJ Full Version ;
; Revision Name ; TestUSB ;
; Top-level Entity Name ; TestUSB ;
; Family ; Cyclone ;
; Total logic elements ; 29 ;
; Total pins ; 19 ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 ;
; Total PLLs ; 0 ;
+-----------------------------+------------------------------------------+
+---------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+--------------------------------------------------------------------+--------------+---------------+
; Option ; Setting ; Default Value ;
+--------------------------------------------------------------------+--------------+---------------+
; Device ; EP1C6Q240C8 ; ;
; Family name ; Cyclone ; Stratix ;
; Use smart compilation ; Normal ; Normal ;
; Restructure Multiplexers ; Auto ; Auto ;
; Create Debugging Nodes for IP Cores ; off ; off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; Top-level entity name ; TestUSB ; TestUSB ;
; State Machine Processing ; Auto ; Auto ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique -- Cyclone ; Balanced ; Balanced ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Remove Duplicate Logic ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Perform gate-level register retiming ; Off ; Off ;
; Allow register retiming to trade off Tsu/Tco with Fmax ; On ; On ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto Shift Register Replacement ; On ; On ;
; Auto Clock Enable Replacement ; On ; On ;
; Allows Synchronous Control Signal Usage in Normal Mode Logic Cells ; On ; On ;
; Auto RAM Block Balancing ; On ; On ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Enable M512 Memory Blocks ; On ; On ;
+--------------------------------------------------------------------+--------------+---------------+
+-----------+
; Hierarchy ;
+-----------+
TestUSB
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; |TestUSB ; 29 (29) ; 16 ; 0 ; 19 ; 0 ; 13 (13) ; 16 (16) ; 0 (0) ; 0 (0) ; |TestUSB ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in G:/ezNiosC6C/TestUSB/TestUSB.map.eqn.
+-------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+--------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Name with Absolute Path ;
+----------------------------------+-----------------+--------------------------------+
; testusb.v ; yes ; G:/ezNiosC6C/TestUSB/testusb.v ;
+----------------------------------+-----------------+--------------------------------+
+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------+-----------+
; Resource ; Usage ;
+---------------------------------+-----------+
; Logic cells ; 29 ;
; Total combinational functions ; 13 ;
; Total 4-input functions ; 8 ;
; Total 3-input functions ; 1 ;
; Total 2-input functions ; 4 ;
; Total 1-input functions ; 0 ;
; Total 0-input functions ; 0 ;
; Combinational cells for routing ; 0 ;
; Total registers ; 16 ;
; I/O pins ; 19 ;
; Maximum fan-out node ; RESET_ ;
; Maximum fan-out ; 16 ;
; Total fan-out ; 111 ;
; Average fan-out ; 2.31 ;
+---------------------------------+-----------+
+----------------------------------------------------------------+
; WYSIWYG Cells ;
+--------------------------------------------------------+-------+
; Statistic ; Value ;
+--------------------------------------------------------+-------+
; Number of WYSIWYG cells ; 0 ;
; Number of synthesis-generated cells ; 29 ;
; Number of WYSIWYG LUTs ; 0 ;
; Number of synthesis-generated LUTs ; 13 ;
; Number of WYSIWYG registers ; 0 ;
; Number of synthesis-generated registers ; 16 ;
; Number of cells with combinational logic only ; 13 ;
; Number of cells with registers only ; 16 ;
; Number of cells with combinational logic and registers ; 0 ;
+--------------------------------------------------------+-------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 16 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 16 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Output Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
Info: Processing started: Wed Oct 24 19:39:56 2007
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off TestUSB -c TestUSB
Info: Found 1 design units, including 1 entities, in source file testusb.v
Info: Found entity 1: TestUSB
Warning: Output pins are stuck at VCC or GND
Warning: Pin "USB_INT_" stuck at VCC
Warning: Pin "SDRAM_CS_" stuck at VCC
Warning: Pin "FLASH_CE_" stuck at VCC
Info: Implemented 48 device resources after synthesis - the final resource count might be different
Info: Implemented 4 input pins
Info: Implemented 7 output pins
Info: Implemented 8 bidirectional pins
Info: Implemented 29 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings
Info: Processing ended: Wed Oct 24 19:39:58 2007
Info: Elapsed time: 00:00:03
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