keyboard_tb.vhd

vhdl编写的4X4键盘扫描程序

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-- Company: 
-- Engineer:
--
-- Create Date:   17:27:11 08/31/2007
-- Design Name:   keyboard
-- Module Name:   keyboard_tb.vhd
-- Project Name:  keylcd
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: keyboard
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY keyboard_tb_vhd IS
END keyboard_tb_vhd;

ARCHITECTURE behavior OF keyboard_tb_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT keyboard
	Port ( KB_ROW : buffer 	std_logic_vector(3 downto 0);
          KB_COL : in	 	std_logic_vector(3 downto 0);
          KB_CLK	: in 		std_logic;
          KB_RST	: in 		std_logic;
          KB_VAL : out 	std_logic_vector(7 downto 0);
	    	  KB_VLD	: out 	std_logic;
          KB_BLL : out 	std_logic);
	END COMPONENT;

	--Inputs
	SIGNAL KB_CLK :  std_logic := '0';
	SIGNAL KB_RST :  std_logic := '0';
	SIGNAL KB_RST1 :  std_logic := '0';

	--BiDirs
	SIGNAL KB_ROW :  std_logic_vector(3 downto 0);
	SIGNAL KB_COL :  std_logic_vector(3 downto 0);

	--Outputs
	SIGNAL KB_VAL :  std_logic_vector(7 downto 0);
	SIGNAL KB_VLD :  std_logic;
	SIGNAL KB_BLL:  std_logic;
	SIGNAL KCNT   :  std_logic_vector(15 downto 0);

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: keyboard PORT MAP(
		KB_ROW => KB_ROW,
		KB_COL => KB_COL,
		KB_CLK => KB_CLK,
		KB_RST => KB_RST,
		KB_VAL => KB_VAL,
		KB_VLD => KB_VLD,
		KB_BLL => KB_BLL
	);

	tb : PROCESS
	BEGIN

		-- Wait 100 ns for global reset to finish
		wait for 100 ns;

		-- Place stimulus here
		KB_RST1 <= '1';
		wait for 40ns;
		KB_RST <= '0';
		wait for 40ns;
		KB_RST <= '1';
		wait for 800ns;

		wait; -- will wait forever
	END PROCESS;

	tb1: process
	begin
		wait for 100ns;
		while true loop
			KB_CLK <= '0','1' after 15ns;
			wait for 30ns;
		end loop;

		wait; -- will wait forever
	end process;

	tb2: process(KB_CLK,KB_RST)
	begin
	   if(KB_RST = '0') then
	      KCNT <= X"0000";
		elsif(KB_CLK'event and KB_CLK = '0') then
		   KCNT <= KCNT+1;
			case KCNT(15 downto 8) is
				when "00000000" =>
					case KB_ROW is
						when X"E" => KB_COL <= X"F";
						when X"D" => KB_COL <= X"F";
						when X"B" => KB_COL <= X"F";
						when X"7" => KB_COL <= X"E";
						when others =>
						    KB_COL <= X"F";
					end case;
				
				when "00000001" =>
					KB_COL <= X"F";					

				when "00000010" =>
					case KB_ROW is
						when X"E" => KB_COL <= X"F";
						when X"D" => KB_COL <= X"E";
						when X"B" => KB_COL <= X"F";
						when X"7" => KB_COL <= X"F";
						when others =>
						    KB_COL <= X"F";
					end case;

				when "00000011" =>
					case KB_ROW is
						when X"E" => KB_COL <= X"F";
						when X"D" => KB_COL <= X"F";
						when X"B" => KB_COL <= X"E";
						when X"7" => KB_COL <= X"F";
						when others =>
						    KB_COL <= X"F";
					end case;
				when others =>
						KB_COL <= X"F";
			end case;
		end if;
	end process;

END;