tcontroller2.v

来自「一个用verilog语言编写的用来模拟交通信号灯的程序」· Verilog 代码 · 共 68 行

module Tcontroller2(green,yellow,red,clk,reset);
	output green,yellow,red;
	input clk,reset;
	wire green,yellow,red;
	reg [5:0] counter;
	reg [2:0] state;
	
	always @ (posedge clk or negedge reset)
		begin
			if (!reset)
				begin
					counter <= 0;
					state <= 0;
				end
			else
			case(state)
				0:state <= 1;
				1://green
				begin
					if (counter == 24)
						begin
							state <= 2;
							counter <= 0;
						end
					else
						begin
							counter <= counter + 1;
						end
				end
				2://yellow
				begin
					if (counter == 1)
						begin
							state <= 3;
							counter <= 0;
						end
					else
						begin
							counter <= counter + 1;
						end
				end
				3://red
				begin
					if (counter == 14)
						begin
							state <= 1;
							counter <= 0;
						end
					else
						begin
							counter <= counter + 1;
						end
				end
				default:
					begin
						state <= 0;
					end
			endcase
		end

assign green  = (state==1)?1:0;
assign yellow = (state==2)?1:0;
assign red    = (state==3)?1:0;


endmodule