mc68hc908jb16.inc

bdm源代码. coldfire处理器用

mT1CH1H_BIT13:      equ    %00100000
mT1CH1H_BIT14:      equ    %01000000
mT1CH1H_BIT15:      equ    %10000000


;*** T1CH1L - TIM Channel 1 Register Low; 0x00000015 ***
T1CH1L:             equ    $00000015                                ;*** T1CH1L - TIM Channel 1 Register Low; 0x00000015 ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
T1CH1L_BIT0:        equ    0                                         ; TIM1 Channel Register BIT 0
T1CH1L_BIT1:        equ    1                                         ; TIM1 Channel Register BIT 1
T1CH1L_BIT2:        equ    2                                         ; TIM1 Channel Register BIT 2
T1CH1L_BIT3:        equ    3                                         ; TIM1 Channel Register BIT 3
T1CH1L_BIT4:        equ    4                                         ; TIM1 Channel Register BIT 4
T1CH1L_BIT5:        equ    5                                         ; TIM1 Channel Register BIT 5
T1CH1L_BIT6:        equ    6                                         ; TIM1 Channel Register BIT 6
T1CH1L_BIT7:        equ    7                                         ; TIM1 Channel Register BIT 7
; bit position masks
mT1CH1L_BIT0:       equ    %00000001
mT1CH1L_BIT1:       equ    %00000010
mT1CH1L_BIT2:       equ    %00000100
mT1CH1L_BIT3:       equ    %00001000
mT1CH1L_BIT4:       equ    %00010000
mT1CH1L_BIT5:       equ    %00100000
mT1CH1L_BIT6:       equ    %01000000
mT1CH1L_BIT7:       equ    %10000000


;*** KBSCR - Keyboard Status and Control Register; 0x00000016 ***
KBSCR:              equ    $00000016                                ;*** KBSCR - Keyboard Status and Control Register; 0x00000016 ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
KBSCR_MODEK:        equ    0                                         ; Keyboard Triggering Sensitivity Bit
KBSCR_IMASKK:       equ    1                                         ; Keyboard Interrupt Mask Bit
KBSCR_ACKK:         equ    2                                         ; Keyboard Acknowledge Bit
KBSCR_KEYF:         equ    3                                         ; Keyboard Flag Bit
; bit position masks
mKBSCR_MODEK:       equ    %00000001
mKBSCR_IMASKK:      equ    %00000010
mKBSCR_ACKK:        equ    %00000100
mKBSCR_KEYF:        equ    %00001000


;*** KBIER - Keyboard Interrrupt Enable Register KBIER; 0x00000017 ***
KBIER:              equ    $00000017                                ;*** KBIER - Keyboard Interrrupt Enable Register KBIER; 0x00000017 ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
KBIER_KBIE0:        equ    0                                         ; Keyboard Interrupt Enable Bit 0
KBIER_KBIE1:        equ    1                                         ; Keyboard Interrupt Enable Bit 1
KBIER_KBIE2:        equ    2                                         ; Keyboard Interrupt Enable Bit 2
KBIER_KBIE3:        equ    3                                         ; Keyboard Interrupt Enable Bit 3
KBIER_KBIE4:        equ    4                                         ; Keyboard Interrupt Enable Bit 4
KBIER_KBIE5:        equ    5                                         ; Keyboard Interrupt Enable Bit 5
KBIER_KBIE6:        equ    6                                         ; Keyboard Interrupt Enable Bit 6
KBIER_KBIE7:        equ    7                                         ; Keyboard Interrupt Enable Bit 7
; bit position masks
mKBIER_KBIE0:       equ    %00000001
mKBIER_KBIE1:       equ    %00000010
mKBIER_KBIE2:       equ    %00000100
mKBIER_KBIE3:       equ    %00001000
mKBIER_KBIE4:       equ    %00010000
mKBIER_KBIE5:       equ    %00100000
mKBIER_KBIE6:       equ    %01000000
mKBIER_KBIE7:       equ    %10000000


;*** UIR2 - USB Interrupt Register 2; 0x00000018 ***
UIR2:               equ    $00000018                                ;*** UIR2 - USB Interrupt Register 2; 0x00000018 ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
UIR2_RXD0FR:        equ    0                                         ; Endpoint 0 Receive Flag Reset
UIR2_TXD0FR:        equ    1                                         ; Endpoint 0 Transmit Flag Reset
UIR2_RESUMFR:       equ    2                                         ; Resume Flag Reset
UIR2_TXD1FR:        equ    3                                         ; Endpoint 1 Transmit Flag Reset
UIR2_RXD2FR:        equ    4                                         ; Endpoint 2 Receive Flag Reset
UIR2_TXD2FR:        equ    5                                         ; Endpoint 2 Transmit Flag Reset
UIR2_RSTFR:         equ    6                                         ; Clear Reset Indicator Bit
UIR2_EOPFR:         equ    7                                         ; End-of-Packet Flag Reset
; bit position masks
mUIR2_RXD0FR:       equ    %00000001
mUIR2_TXD0FR:       equ    %00000010
mUIR2_RESUMFR:      equ    %00000100
mUIR2_TXD1FR:       equ    %00001000
mUIR2_RXD2FR:       equ    %00010000
mUIR2_TXD2FR:       equ    %00100000
mUIR2_RSTFR:        equ    %01000000
mUIR2_EOPFR:        equ    %10000000


;*** UCR2 - USB Control Register 2; 0x00000019 ***
UCR2:               equ    $00000019                                ;*** UCR2 - USB Control Register 2; 0x00000019 ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
UCR2_TP2SIZ0:       equ    0                                         ; Endpoint 2 Transmit Data Packet Size Bit 0
UCR2_TP2SIZ1:       equ    1                                         ; Endpoint 2 Transmit Data Packet Size Bit 1
UCR2_TP2SIZ2:       equ    2                                         ; Endpoint 2 Transmit Data Packet Size Bit 2
UCR2_TP2SIZ3:       equ    3                                         ; Endpoint 2 Transmit Data Packet Size Bit 3
UCR2_RX2E:          equ    4                                         ; Endpoint 2 Receive Enable
UCR2_TX2E:          equ    5                                         ; Endpoint 2 Transmit Enable
UCR2_STALL:         equ    6                                         ; Endpoint 2 Force Stall Bit
UCR2_T2SEQ:         equ    7                                         ; Endpoint 2 Transmit Sequence Bit
; bit position masks
mUCR2_TP2SIZ0:      equ    %00000001
mUCR2_TP2SIZ1:      equ    %00000010
mUCR2_TP2SIZ2:      equ    %00000100
mUCR2_TP2SIZ3:      equ    %00001000
mUCR2_RX2E:         equ    %00010000
mUCR2_TX2E:         equ    %00100000
mUCR2_STALL:        equ    %01000000
mUCR2_T2SEQ:        equ    %10000000


;*** UCR3 - USB Control Register 3; 0x0000001A ***
UCR3:               equ    $0000001A                                ;*** UCR3 - USB Control Register 3; 0x0000001A ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
UCR3_ENABLE1:       equ    0                                         ; Endpoint 1 Enable
UCR3_ENABLE2:       equ    1                                         ; Endpoint 2 Enable
UCR3_PULLEN:        equ    2                                         ; Pull-up Enable
UCR3_ISTALL0:       equ    4                                         ; Endpoint 0 Force STALL Bit for IN token
UCR3_OSTALL0:       equ    5                                         ; Endpoint 0 Force STALL Bit for OUT token
UCR3_TX1STR:        equ    6                                         ; Clear Endpoint 0 Transmit First Flag
UCR3_TX1ST:         equ    7                                         ; Endpoint 0 Transmit First Flag
; bit position masks
mUCR3_ENABLE1:      equ    %00000001
mUCR3_ENABLE2:      equ    %00000010
mUCR3_PULLEN:       equ    %00000100
mUCR3_ISTALL0:      equ    %00010000
mUCR3_OSTALL0:      equ    %00100000
mUCR3_TX1STR:       equ    %01000000
mUCR3_TX1ST:        equ    %10000000


;*** UCR4 - USB Control Register 4; 0x0000001B ***
UCR4:               equ    $0000001B                                ;*** UCR4 - USB Control Register 4; 0x0000001B ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
UCR4_FDM:           equ    0                                         ; Force D-
UCR4_FDP:           equ    1                                         ; Force D+
UCR4_FUSBO:         equ    2                                         ; Force USB Output
; bit position masks
mUCR4_FDM:          equ    %00000001
mUCR4_FDP:          equ    %00000010
mUCR4_FUSBO:        equ    %00000100


;*** IOCR - IRQ Option Register; 0x0000001C ***
IOCR:               equ    $0000001C                                ;*** IOCR - IRQ Option Register; 0x0000001C ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
IOCR_IRQPD:         equ    0                                         ; IRQ Pullup Disable
IOCR_PTE4IE:        equ    1                                         ; PTE4 Interrupt Enable
IOCR_PTE4IF:        equ    2                                         ; PTE4 Interrupt Flag
; bit position masks
mIOCR_IRQPD:        equ    %00000001
mIOCR_PTE4IE:       equ    %00000010
mIOCR_PTE4IF:       equ    %00000100


;*** POCR - Port Option Control Register; 0x0000001D ***
POCR:               equ    $0000001D                                ;*** POCR - Port Option Control Register; 0x0000001D ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
POCR_PAP:           equ    0                                         ; Port A Pullup Enable
POCR_PCP:           equ    2                                         ; Port C Pullup Enable
POCR_PTE3P:         equ    3                                         ; Pin PTE3 Pullup Enable
POCR_PTE4P:         equ    4                                         ; Pin PTE4 Pullup Enable
POCR_PTDILDD:       equ    5                                         ; Infrared LED Drive Control
POCR_PTDLDD:        equ    6                                         ; LED Direct Drive Control
POCR_PTE20P:        equ    7                                         ; Pins PTE[2:0] Pullup Enable
; bit position masks
mPOCR_PAP:          equ    %00000001
mPOCR_PCP:          equ    %00000100
mPOCR_PTE3P:        equ    %00001000
mPOCR_PTE4P:        equ    %00010000
mPOCR_PTDILDD:      equ    %00100000
mPOCR_PTDLDD:       equ    %01000000
mPOCR_PTE20P:       equ    %10000000


;*** ISCR - IRQ Status and Control Register; 0x0000001E ***
ISCR:               equ    $0000001E                                ;*** ISCR - IRQ Status and Control Register; 0x0000001E ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
ISCR_MODE:          equ    0                                         ; IRQ Edge/Level Select Bit
ISCR_IMASK:         equ    1                                         ; IRQ Interrupt Mask Bit
ISCR_ACK:           equ    2                                         ; IRQ Interrupt Request Acknowledge Bit
ISCR_IRQF:          equ    3                                         ; IRQ Flag Bit
; bit position masks
mISCR_MODE:         equ    %00000001
mISCR_IMASK:        equ    %00000010
mISCR_ACK:          equ    %00000100
mISCR_IRQF:         equ    %00001000


;*** CONFIG - Configuration Register; 0x0000001F ***
CONFIG:             equ    $0000001F                                ;*** CONFIG - Configuration Register; 0x0000001F ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
CONFIG_COPD:        equ    0                                         ; COP Disable Bit
CONFIG_STOP:        equ    1                                         ; STOP Instruction Enable Bit
CONFIG_COPRS:       equ    2                                         ; COP Reset Period Selection Bit
CONFIG_SSREC:       equ    3                                         ; Short Stop Recovery Bit
CONFIG_LVID:        equ    4                                         ; Low Voltage Inhibit Disable Bit
CONFIG_URSTD:       equ    5                                         ; USB Reset Disable Bit
CONFIG_LVI5OR3:     equ    6                                         ; LVI Trip Point Voltage Select Bit for Vdd
CONFIG_LVIDR:       equ    7                                         ; LVI Disable Bit for Vreg
; bit position masks
mCONFIG_COPD:       equ    %00000001
mCONFIG_STOP:       equ    %00000010
mCONFIG_COPRS:      equ    %00000100
mCONFIG_SSREC:      equ    %00001000
mCONFIG_LVID:       equ    %00010000
mCONFIG_URSTD:      equ    %00100000