📄 mc68hc908jb16.inc
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;*** T1CNTH - TIM Counter Register Low; 0x0000000C ***
T1CNTH: equ $0000000C ;*** T1CNTH - TIM Counter Register Low; 0x0000000C ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
T1CNTH_BIT8: equ 0 ; TIM1 Counter Bit
T1CNTH_BIT9: equ 1 ; TIM1 Counter Bit
T1CNTH_BIT10: equ 2 ; TIM1 Counter Bit
T1CNTH_BIT11: equ 3 ; TIM1 Counter Bit
T1CNTH_BIT12: equ 4 ; TIM1 Counter Bit
T1CNTH_BIT13: equ 5 ; TIM1 Counter Bit
T1CNTH_BIT14: equ 6 ; TIM1 Counter Bit
T1CNTH_BIT15: equ 7 ; TIM1 Counter Bit
; bit position masks
mT1CNTH_BIT8: equ %00000001
mT1CNTH_BIT9: equ %00000010
mT1CNTH_BIT10: equ %00000100
mT1CNTH_BIT11: equ %00001000
mT1CNTH_BIT12: equ %00010000
mT1CNTH_BIT13: equ %00100000
mT1CNTH_BIT14: equ %01000000
mT1CNTH_BIT15: equ %10000000
;*** T1CNTL - TIM Counter Register Low; 0x0000000D ***
T1CNTL: equ $0000000D ;*** T1CNTL - TIM Counter Register Low; 0x0000000D ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
T1CNTL_BIT0: equ 0 ; TIM1 Counter Bit
T1CNTL_BIT1: equ 1 ; TIM1 Counter Bit
T1CNTL_BIT2: equ 2 ; TIM1 Counter Bit
T1CNTL_BIT3: equ 3 ; TIM1 Counter Bit
T1CNTL_BIT4: equ 4 ; TIM1 Counter Bit
T1CNTL_BIT5: equ 5 ; TIM1 Counter Bit
T1CNTL_BIT6: equ 6 ; TIM1 Counter Bit
T1CNTL_BIT7: equ 7 ; TIM1 Counter Bit
; bit position masks
mT1CNTL_BIT0: equ %00000001
mT1CNTL_BIT1: equ %00000010
mT1CNTL_BIT2: equ %00000100
mT1CNTL_BIT3: equ %00001000
mT1CNTL_BIT4: equ %00010000
mT1CNTL_BIT5: equ %00100000
mT1CNTL_BIT6: equ %01000000
mT1CNTL_BIT7: equ %10000000
;*** T1MOD - TIM Counter Modulo Register; 0x0000000E ***
T1MOD: equ $0000000E ;*** T1MOD - TIM Counter Modulo Register; 0x0000000E ***
;*** T1MODH - TIM Counter Modulo Register High; 0x0000000E ***
T1MODH: equ $0000000E ;*** T1MODH - TIM Counter Modulo Register High; 0x0000000E ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
T1MODH_BIT8: equ 0 ; TIM1 Counter Modulo Bit
T1MODH_BIT9: equ 1 ; TIM1 Counter Modulo Bit
T1MODH_BIT10: equ 2 ; TIM1 Counter Modulo Bit
T1MODH_BIT11: equ 3 ; TIM1 Counter Modulo Bit
T1MODH_BIT12: equ 4 ; TIM1 Counter Modulo Bit
T1MODH_BIT13: equ 5 ; TIM1 Counter Modulo Bit
T1MODH_BIT14: equ 6 ; TIM1 Counter Modulo Bit
T1MODH_BIT15: equ 7 ; TIM1 Counter Modulo Bit
; bit position masks
mT1MODH_BIT8: equ %00000001
mT1MODH_BIT9: equ %00000010
mT1MODH_BIT10: equ %00000100
mT1MODH_BIT11: equ %00001000
mT1MODH_BIT12: equ %00010000
mT1MODH_BIT13: equ %00100000
mT1MODH_BIT14: equ %01000000
mT1MODH_BIT15: equ %10000000
;*** T1MODL - TIM Counter Modulo Register Low; 0x0000000F ***
T1MODL: equ $0000000F ;*** T1MODL - TIM Counter Modulo Register Low; 0x0000000F ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
T1MODL_BIT0: equ 0 ; TIM1 Counter Modulo Bit
T1MODL_BIT1: equ 1 ; TIM1 Counter Modulo Bit
T1MODL_BIT2: equ 2 ; TIM1 Counter Modulo Bit
T1MODL_BIT3: equ 3 ; TIM1 Counter Modulo Bit
T1MODL_BIT4: equ 4 ; TIM1 Counter Modulo Bit
T1MODL_BIT5: equ 5 ; TIM1 Counter Modulo Bit
T1MODL_BIT6: equ 6 ; TIM1 Counter Modulo Bit
T1MODL_BIT7: equ 7 ; TIM1 Counter Modulo Bit
; bit position masks
mT1MODL_BIT0: equ %00000001
mT1MODL_BIT1: equ %00000010
mT1MODL_BIT2: equ %00000100
mT1MODL_BIT3: equ %00001000
mT1MODL_BIT4: equ %00010000
mT1MODL_BIT5: equ %00100000
mT1MODL_BIT6: equ %01000000
mT1MODL_BIT7: equ %10000000
;*** T1SC0 - TIM Channel 0 Status and Control Register; 0x00000010 ***
T1SC0: equ $00000010 ;*** T1SC0 - TIM Channel 0 Status and Control Register; 0x00000010 ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
T1SC0_CH0MAX: equ 0 ; Channel 0 Maximum Duty Cycle Bit
T1SC0_TOV0: equ 1 ; Toggle-On-Overflow Bit
T1SC0_ELS0A: equ 2 ; Edge/Level Select Bit
T1SC0_ELS0B: equ 3 ; Edge/Level Select Bit
T1SC0_MS0A: equ 4 ; Mode Select Bit A
T1SC0_MS0B: equ 5 ; Mode Select Bit B
T1SC0_CH0IE: equ 6 ; Channel 0 Interrupt Enable Bit
T1SC0_CH0F: equ 7 ; Channel 0 Flag Bit
; bit position masks
mT1SC0_CH0MAX: equ %00000001
mT1SC0_TOV0: equ %00000010
mT1SC0_ELS0A: equ %00000100
mT1SC0_ELS0B: equ %00001000
mT1SC0_MS0A: equ %00010000
mT1SC0_MS0B: equ %00100000
mT1SC0_CH0IE: equ %01000000
mT1SC0_CH0F: equ %10000000
;*** T1CH0 - TIM Channel 0 Register; 0x00000011 ***
T1CH0: equ $00000011 ;*** T1CH0 - TIM Channel 0 Register; 0x00000011 ***
;*** T1CH0H - TIM Channel 0 Register High; 0x00000011 ***
T1CH0H: equ $00000011 ;*** T1CH0H - TIM Channel 0 Register High; 0x00000011 ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
T1CH0H_BIT8: equ 0 ; TIM1 Channel Register BIT 8
T1CH0H_BIT9: equ 1 ; TIM1 Channel Register BIT 9
T1CH0H_BIT10: equ 2 ; TIM1 Channel Register BIT 10
T1CH0H_BIT11: equ 3 ; TIM1 Channel Register BIT 11
T1CH0H_BIT12: equ 4 ; TIM1 Channel Register BIT 12
T1CH0H_BIT13: equ 5 ; TIM1 Channel Register BIT 13
T1CH0H_BIT14: equ 6 ; TIM1 Channel Register BIT 14
T1CH0H_BIT15: equ 7 ; TIM1 Channel Register BIT 15
; bit position masks
mT1CH0H_BIT8: equ %00000001
mT1CH0H_BIT9: equ %00000010
mT1CH0H_BIT10: equ %00000100
mT1CH0H_BIT11: equ %00001000
mT1CH0H_BIT12: equ %00010000
mT1CH0H_BIT13: equ %00100000
mT1CH0H_BIT14: equ %01000000
mT1CH0H_BIT15: equ %10000000
;*** T1CH0L - TIM Channel 0 Register Low; 0x00000012 ***
T1CH0L: equ $00000012 ;*** T1CH0L - TIM Channel 0 Register Low; 0x00000012 ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
T1CH0L_BIT0: equ 0 ; TIM1 Channel Register BIT 0
T1CH0L_BIT1: equ 1 ; TIM1 Channel Register BIT 1
T1CH0L_BIT2: equ 2 ; TIM1 Channel Register BIT 2
T1CH0L_BIT3: equ 3 ; TIM1 Channel Register BIT 3
T1CH0L_BIT4: equ 4 ; TIM1 Channel Register BIT 4
T1CH0L_BIT5: equ 5 ; TIM1 Channel Register BIT 5
T1CH0L_BIT6: equ 6 ; TIM1 Channel Register BIT 6
T1CH0L_BIT7: equ 7 ; TIM1 Channel Register BIT 7
; bit position masks
mT1CH0L_BIT0: equ %00000001
mT1CH0L_BIT1: equ %00000010
mT1CH0L_BIT2: equ %00000100
mT1CH0L_BIT3: equ %00001000
mT1CH0L_BIT4: equ %00010000
mT1CH0L_BIT5: equ %00100000
mT1CH0L_BIT6: equ %01000000
mT1CH0L_BIT7: equ %10000000
;*** T1SC1 - TIM Channel 1 Status and Control Register; 0x00000013 ***
T1SC1: equ $00000013 ;*** T1SC1 - TIM Channel 1 Status and Control Register; 0x00000013 ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
T1SC1_CH1MAX: equ 0 ; Channel 1 Maximum Duty Cycle Bit
T1SC1_TOV1: equ 1 ; Toggle-On-Overflow Bit
T1SC1_ELS1A: equ 2 ; Edge/Level Select Bit
T1SC1_ELS1B: equ 3 ; Edge/Level Select Bit
T1SC1_MS1A: equ 4 ; Mode Select Bit A
T1SC1_CH1IE: equ 6 ; Channel 1 Interrupt Enable Bit
T1SC1_CH1F: equ 7 ; Channel 1 Flag Bit
; bit position masks
mT1SC1_CH1MAX: equ %00000001
mT1SC1_TOV1: equ %00000010
mT1SC1_ELS1A: equ %00000100
mT1SC1_ELS1B: equ %00001000
mT1SC1_MS1A: equ %00010000
mT1SC1_CH1IE: equ %01000000
mT1SC1_CH1F: equ %10000000
;*** T1CH1 - TIM Channel 1 Register; 0x00000014 ***
T1CH1: equ $00000014 ;*** T1CH1 - TIM Channel 1 Register; 0x00000014 ***
;*** T1CH1H - TIM Channel 1 Register High; 0x00000014 ***
T1CH1H: equ $00000014 ;*** T1CH1H - TIM Channel 1 Register High; 0x00000014 ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
T1CH1H_BIT8: equ 0 ; TIM1 Channel Register BIT 8
T1CH1H_BIT9: equ 1 ; TIM1 Channel Register BIT 9
T1CH1H_BIT10: equ 2 ; TIM1 Channel Register BIT 10
T1CH1H_BIT11: equ 3 ; TIM1 Channel Register BIT 11
T1CH1H_BIT12: equ 4 ; TIM1 Channel Register BIT 12
T1CH1H_BIT13: equ 5 ; TIM1 Channel Register BIT 13
T1CH1H_BIT14: equ 6 ; TIM1 Channel Register BIT 14
T1CH1H_BIT15: equ 7 ; TIM1 Channel Register BIT 15
; bit position masks
mT1CH1H_BIT8: equ %00000001
mT1CH1H_BIT9: equ %00000010
mT1CH1H_BIT10: equ %00000100
mT1CH1H_BIT11: equ %00001000
mT1CH1H_BIT12: equ %00010000
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