📄 mc68hc908jb16.inc
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; Based on CPU DB MC68HC908JB16, version 2.89.005 (RegistersPrg V1.061)
; ###################################################################
; Filename : MC68HC908JB16.h
; Processor : MC68HC908JB16
; FileFormat: V1.061
; DataSheet : manual revision not specified
; Compiler : Metrowerks C compiler
; Date/Time : 08.04.2004, 09:15
; Abstract :
; This implements an IO devices mapping.
;
; (c) Copyright UNIS, spol. s r.o. 1997-2003
; UNIS, spol. s r.o.
; Jundrovska 33
; 624 00 Brno
; Czech Republic
; http : www.processorexpert.com
; mail : info@processorexpert.com
; ###################################################################
;*** Memory Map and Interrupt Vectors
;******************************************
ROMStart: equ $0000BA00
ROMEnd: equ $0000F9FF
Z_RAMStart: equ $00000080
Z_RAMEnd: equ $000000FF
RAMStart: equ $00000100
RAMEnd: equ $000001FF
;
INT_KBI: equ $0000FFE0
INT_SCITransmit: equ $0000FFE2
INT_SCIReceive: equ $0000FFE4
INT_SCIError: equ $0000FFE6
INT_TIM2Ovr: equ $0000FFE8
INT_TIM2CH01: equ $0000FFEA
INT_TIM2CH1: equ $0000FFEC
INT_TIM2CH0: equ $0000FFEE
INT_TIM1Ovr: equ $0000FFF0
INT_TIM1CH01: equ $0000FFF2
INT_TIM1CH1: equ $0000FFF4
INT_TIM1CH0: equ $0000FFF6
INT_IRQ: equ $0000FFF8
INT_USB: equ $0000FFFA
INT_SWI: equ $0000FFFC
INT_RESET: equ $0000FFFE
;
;*** PTA - Port A Data Register; 0x00000000 ***
PTA: equ $00000000 ;*** PTA - Port A Data Register; 0x00000000 ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
PTA_PTA0: equ 0 ; Port A Data Bit 0
PTA_PTA1: equ 1 ; Port A Data Bit 1
PTA_PTA2: equ 2 ; Port A Data Bit 2
PTA_PTA3: equ 3 ; Port A Data Bit 3
PTA_PTA4: equ 4 ; Port A Data Bit 4
PTA_PTA5: equ 5 ; Port A Data Bit 5
PTA_PTA6: equ 6 ; Port A Data Bit 6
PTA_PTA7: equ 7 ; Port A Data Bit 7
; bit position masks
mPTA_PTA0: equ %00000001
mPTA_PTA1: equ %00000010
mPTA_PTA2: equ %00000100
mPTA_PTA3: equ %00001000
mPTA_PTA4: equ %00010000
mPTA_PTA5: equ %00100000
mPTA_PTA6: equ %01000000
mPTA_PTA7: equ %10000000
;*** PTC - Port C Data Register; 0x00000002 ***
PTC: equ $00000002 ;*** PTC - Port C Data Register; 0x00000002 ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
PTC_PTC0: equ 0 ; Port C Data Bit 0
PTC_PTC1: equ 1 ; Port C Data Bit 1
; bit position masks
mPTC_PTC0: equ %00000001
mPTC_PTC1: equ %00000010
;*** PTD - Port D Data Register; 0x00000003 ***
PTD: equ $00000003 ;*** PTD - Port D Data Register; 0x00000003 ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
PTD_PTD0: equ 0 ; Port D Data Bit 0
PTD_PTD1: equ 1 ; Port D Data Bit 1
PTD_PTD2: equ 2 ; Port D Data Bit 2
PTD_PTD3: equ 3 ; Port D Data Bit 3
PTD_PTD4: equ 4 ; Port D Data Bit 4
PTD_PTD5: equ 5 ; Port D Data Bit 5
; bit position masks
mPTD_PTD0: equ %00000001
mPTD_PTD1: equ %00000010
mPTD_PTD2: equ %00000100
mPTD_PTD3: equ %00001000
mPTD_PTD4: equ %00010000
mPTD_PTD5: equ %00100000
;*** DDRA - Data Direction Register A; 0x00000004 ***
DDRA: equ $00000004 ;*** DDRA - Data Direction Register A; 0x00000004 ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
DDRA_DDRA0: equ 0 ; Data Direction Register A Bit 0
DDRA_DDRA1: equ 1 ; Data Direction Register A Bit 1
DDRA_DDRA2: equ 2 ; Data Direction Register A Bit 2
DDRA_DDRA3: equ 3 ; Data Direction Register A Bit 3
DDRA_DDRA4: equ 4 ; Data Direction Register A Bit 4
DDRA_DDRA5: equ 5 ; Data Direction Register A Bit 5
DDRA_DDRA6: equ 6 ; Data Direction Register A Bit 6
DDRA_DDRA7: equ 7 ; Data Direction Register A Bit 7
; bit position masks
mDDRA_DDRA0: equ %00000001
mDDRA_DDRA1: equ %00000010
mDDRA_DDRA2: equ %00000100
mDDRA_DDRA3: equ %00001000
mDDRA_DDRA4: equ %00010000
mDDRA_DDRA5: equ %00100000
mDDRA_DDRA6: equ %01000000
mDDRA_DDRA7: equ %10000000
;*** DDRC - Data Direction Register C; 0x00000006 ***
DDRC: equ $00000006 ;*** DDRC - Data Direction Register C; 0x00000006 ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
DDRC_DDRC0: equ 0 ; Data Direction Register C Bit 0
DDRC_DDRC1: equ 1 ; Data Direction Register C Bit 1
; bit position masks
mDDRC_DDRC0: equ %00000001
mDDRC_DDRC1: equ %00000010
;*** DDRD - Data Direction Register D; 0x00000007 ***
DDRD: equ $00000007 ;*** DDRD - Data Direction Register D; 0x00000007 ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
DDRD_DDRD0: equ 0 ; Data Direction Register D Bit 0
DDRD_DDRD1: equ 1 ; Data Direction Register D Bit 1
DDRD_DDRD2: equ 2 ; Data Direction Register D Bit 2
DDRD_DDRD3: equ 3 ; Data Direction Register D Bit 3
DDRD_DDRD4: equ 4 ; Data Direction Register D Bit 4
DDRD_DDRD5: equ 5 ; Data Direction Register D Bit 5
; bit position masks
mDDRD_DDRD0: equ %00000001
mDDRD_DDRD1: equ %00000010
mDDRD_DDRD2: equ %00000100
mDDRD_DDRD3: equ %00001000
mDDRD_DDRD4: equ %00010000
mDDRD_DDRD5: equ %00100000
;*** PTE - Port E Data Register; 0x00000008 ***
PTE: equ $00000008 ;*** PTE - Port E Data Register; 0x00000008 ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
PTE_PTE0: equ 0 ; Port E Data Bit 0
PTE_PTE1: equ 1 ; Port E Data Bit 1
PTE_PTE2: equ 2 ; Port E Data Bit 2
PTE_PTE3: equ 3 ; Port E Data Bit 3
PTE_PTE4: equ 4 ; Port E Data Bit 4
; bit position masks
mPTE_PTE0: equ %00000001
mPTE_PTE1: equ %00000010
mPTE_PTE2: equ %00000100
mPTE_PTE3: equ %00001000
mPTE_PTE4: equ %00010000
;*** DDRE - Data Direction Register E; 0x00000009 ***
DDRE: equ $00000009 ;*** DDRE - Data Direction Register E; 0x00000009 ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
DDRE_DDRE0: equ 0 ; Data Direction Register E Bit 0
DDRE_DDRE1: equ 1 ; Data Direction Register E Bit 1
DDRE_DDRE2: equ 2 ; Data Direction Register E Bit 2
DDRE_DDRE3: equ 3 ; Data Direction Register E Bit 3
DDRE_DDRE4: equ 4 ; Data Direction Register E Bit 4
; bit position masks
mDDRE_DDRE0: equ %00000001
mDDRE_DDRE1: equ %00000010
mDDRE_DDRE2: equ %00000100
mDDRE_DDRE3: equ %00001000
mDDRE_DDRE4: equ %00010000
;*** T1SC - TIM Status and Control Register TSC; 0x0000000A ***
T1SC: equ $0000000A ;*** T1SC - TIM Status and Control Register TSC; 0x0000000A ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
T1SC_PS0: equ 0 ; Prescaler Select Bit
T1SC_PS1: equ 1 ; Prescaler Select Bit
T1SC_PS2: equ 2 ; Prescaler Select Bit
T1SC_TRST: equ 4 ; TIM1 Reset Bit
T1SC_TSTOP: equ 5 ; TIM1 Stop Bit
T1SC_TOIE: equ 6 ; TIM1 Overflow Interrupt Enable Bit
T1SC_TOF: equ 7 ; TIM1 Overflow Flag Bit
; bit position masks
mT1SC_PS0: equ %00000001
mT1SC_PS1: equ %00000010
mT1SC_PS2: equ %00000100
mT1SC_TRST: equ %00010000
mT1SC_TSTOP: equ %00100000
mT1SC_TOIE: equ %01000000
mT1SC_TOF: equ %10000000
;*** T1CNT - TIM Counter Register; 0x0000000C ***
T1CNT: equ $0000000C ;*** T1CNT - TIM Counter Register; 0x0000000C ***
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