prev_cmp_i2c.tan.qmsg

FPGA使用I2C总线

{ "Info" "ITDB_FULL_TCO_RESULT" "clk seg_data\[1\] writeData_reg\[0\] 17.457 ns register " "Info: tco from clock \"clk\" to destination pin \"seg_data\[1\]\" through register \"writeData_reg\[0\]\" is 17.457 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.344 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 7.344 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 69 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 69; CLK Node = 'clk'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "i2c.vhd" "" { Text "F:/vhdl/i2c总线/i2c.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.294 ns) + CELL(0.918 ns) 7.344 ns writeData_reg\[0\] 2 REG LC_X13_Y8_N1 2 " "Info: 2: + IC(5.294 ns) + CELL(0.918 ns) = 7.344 ns; Loc. = LC_X13_Y8_N1; Fanout = 2; REG Node = 'writeData_reg\[0\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.212 ns" { clk writeData_reg[0] } "NODE_NAME" } } { "i2c.vhd" "" { Text "F:/vhdl/i2c总线/i2c.vhd" 148 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns ( 27.91 % ) " "Info: Total cell delay = 2.050 ns ( 27.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.294 ns ( 72.09 % ) " "Info: Total interconnect delay = 5.294 ns ( 72.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.344 ns" { clk writeData_reg[0] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.344 ns" { clk clk~combout writeData_reg[0] } { 0.000ns 0.000ns 5.294ns } { 0.000ns 1.132ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "i2c.vhd" "" { Text "F:/vhdl/i2c总线/i2c.vhd" 148 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.737 ns + Longest register pin " "Info: + Longest register to pin delay is 9.737 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns writeData_reg\[0\] 1 REG LC_X13_Y8_N1 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X13_Y8_N1; Fanout = 2; REG Node = 'writeData_reg\[0\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { writeData_reg[0] } "NODE_NAME" } } { "i2c.vhd" "" { Text "F:/vhdl/i2c总线/i2c.vhd" 148 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.287 ns) + CELL(0.914 ns) 2.201 ns Mux112~69 2 COMB LC_X12_Y8_N5 7 " "Info: 2: + IC(1.287 ns) + CELL(0.914 ns) = 2.201 ns; Loc. = LC_X12_Y8_N5; Fanout = 7; COMB Node = 'Mux112~69'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.201 ns" { writeData_reg[0] Mux112~69 } "NODE_NAME" } } { "i2c.vhd" "" { Text "F:/vhdl/i2c总线/i2c.vhd" 783 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.880 ns) + CELL(0.740 ns) 4.821 ns Mux119~560 3 COMB LC_X11_Y8_N8 1 " "Info: 3: + IC(1.880 ns) + CELL(0.740 ns) = 4.821 ns; Loc. = LC_X11_Y8_N8; Fanout = 1; COMB Node = 'Mux119~560'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.620 ns" { Mux112~69 Mux119~560 } "NODE_NAME" } } { "i2c.vhd" "" { Text "F:/vhdl/i2c总线/i2c.vhd" 796 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.749 ns) + CELL(0.200 ns) 6.770 ns Mux119~561 4 COMB LC_X11_Y10_N0 1 " "Info: 4: + IC(1.749 ns) + CELL(0.200 ns) = 6.770 ns; Loc. = LC_X11_Y10_N0; Fanout = 1; COMB Node = 'Mux119~561'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.949 ns" { Mux119~560 Mux119~561 } "NODE_NAME" } } { "i2c.vhd" "" { Text "F:/vhdl/i2c总线/i2c.vhd" 796 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.645 ns) + CELL(2.322 ns) 9.737 ns seg_data\[1\] 5 PIN PIN_119 0 " "Info: 5: + IC(0.645 ns) + CELL(2.322 ns) = 9.737 ns; Loc. = PIN_119; Fanout = 0; PIN Node = 'seg_data\[1\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.967 ns" { Mux119~561 seg_data[1] } "NODE_NAME" } } { "i2c.vhd" "" { Text "F:/vhdl/i2c总线/i2c.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.176 ns ( 42.89 % ) " "Info: Total cell delay = 4.176 ns ( 42.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.561 ns ( 57.11 % ) " "Info: Total interconnect delay = 5.561 ns ( 57.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "9.737 ns" { writeData_reg[0] Mux112~69 Mux119~560 Mux119~561 seg_data[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "9.737 ns" { writeData_reg[0] Mux112~69 Mux119~560 Mux119~561 seg_data[1] } { 0.000ns 1.287ns 1.880ns 1.749ns 0.645ns } { 0.000ns 0.914ns 0.740ns 0.200ns 2.322ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.344 ns" { clk writeData_reg[0] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.344 ns" { clk clk~combout writeData_reg[0] } { 0.000ns 0.000ns 5.294ns } { 0.000ns 1.132ns 0.918ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "9.737 ns" { writeData_reg[0] Mux112~69 Mux119~560 Mux119~561 seg_data[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "9.737 ns" { writeData_reg[0] Mux112~69 Mux119~560 Mux119~561 seg_data[1] } { 0.000ns 1.287ns 1.880ns 1.749ns 0.645ns } { 0.000ns 0.914ns 0.740ns 0.200ns 2.322ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "readData_reg\[0\] sda clk 2.827 ns register " "Info: th for register \"readData_reg\[0\]\" (data pin = \"sda\", clock pin = \"clk\") is 2.827 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.344 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 7.344 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 69 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 69; CLK Node = 'clk'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "i2c.vhd" "" { Text "F:/vhdl/i2c总线/i2c.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.294 ns) + CELL(0.918 ns) 7.344 ns readData_reg\[0\] 2 REG LC_X12_Y8_N5 2 " "Info: 2: + IC(5.294 ns) + CELL(0.918 ns) = 7.344 ns; Loc. = LC_X12_Y8_N5; Fanout = 2; REG Node = 'readData_reg\[0\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.212 ns" { clk readData_reg[0] } "NODE_NAME" } } { "i2c.vhd" "" { Text "F:/vhdl/i2c总线/i2c.vhd" 148 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns ( 27.91 % ) " "Info: Total cell delay = 2.050 ns ( 27.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.294 ns ( 72.09 % ) " "Info: Total interconnect delay = 5.294 ns ( 72.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.344 ns" { clk readData_reg[0] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.344 ns" { clk clk~combout readData_reg[0] } { 0.000ns 0.000ns 5.294ns } { 0.000ns 1.132ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "i2c.vhd" "" { Text "F:/vhdl/i2c总线/i2c.vhd" 148 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.738 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.738 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sda 1 PIN PIN_78 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_78; Fanout = 1; PIN Node = 'sda'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { sda } "NODE_NAME" } } { "i2c.vhd" "" { Text "F:/vhdl/i2c总线/i2c.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns sda~1 2 COMB IOC_X17_Y3_N2 5 " "Info: 2: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = IOC_X17_Y3_N2; Fanout = 5; COMB Node = 'sda~1'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.132 ns" { sda sda~1 } "NODE_NAME" } } { "i2c.vhd" "" { Text "F:/vhdl/i2c总线/i2c.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.326 ns) + CELL(0.280 ns) 4.738 ns readData_reg\[0\] 3 REG LC_X12_Y8_N5 2 " "Info: 3: + IC(3.326 ns) + CELL(0.280 ns) = 4.738 ns; Loc. = LC_X12_Y8_N5; Fanout = 2; REG Node = 'readData_reg\[0\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.606 ns" { sda~1 readData_reg[0] } "NODE_NAME" } } { "i2c.vhd" "" { Text "F:/vhdl/i2c总线/i2c.vhd" 148 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.412 ns ( 29.80 % ) " "Info: Total cell delay = 1.412 ns ( 29.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.326 ns ( 70.20 % ) " "Info: Total interconnect delay = 3.326 ns ( 70.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.738 ns" { sda sda~1 readData_reg[0] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.738 ns" { sda sda~1 readData_reg[0] } { 0.000ns 0.000ns 3.326ns } { 0.000ns 1.132ns 0.280ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.344 ns" { clk readData_reg[0] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.344 ns" { clk clk~combout readData_reg[0] } { 0.000ns 0.000ns 5.294ns } { 0.000ns 1.132ns 0.918ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.738 ns" { sda sda~1 readData_reg[0] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.738 ns" { sda sda~1 readData_reg[0] } { 0.000ns 0.000ns 3.326ns } { 0.000ns 1.132ns 0.280ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "109 " "Info: Allocated 109 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 09 17:44:27 2007 " "Info: Processing ended: Tue Oct 09 17:44:27 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Info: Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}