prev_cmp_i2c.tan.qmsg

FPGA使用I2C总线

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "i2c.vhd" "" { Text "F:/vhdl/i2c总线/i2c.vhd" 15 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register inner_state\[2\] register sda_buf 87.63 MHz 11.412 ns Internal " "Info: Clock \"clk\" has Internal fmax of 87.63 MHz between source register \"inner_state\[2\]\" and destination register \"sda_buf\" (period= 11.412 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.703 ns + Longest register register " "Info: + Longest register to register delay is 10.703 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns inner_state\[2\] 1 REG LC_X11_Y5_N7 25 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X11_Y5_N7; Fanout = 25; REG Node = 'inner_state\[2\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { inner_state[2] } "NODE_NAME" } } { "i2c.vhd" "" { Text "F:/vhdl/i2c总线/i2c.vhd" 148 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.284 ns) + CELL(0.511 ns) 2.795 ns Mux0~396 2 COMB LC_X11_Y7_N7 1 " "Info: 2: + IC(2.284 ns) + CELL(0.511 ns) = 2.795 ns; Loc. = LC_X11_Y7_N7; Fanout = 1; COMB Node = 'Mux0~396'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.795 ns" { inner_state[2] Mux0~396 } "NODE_NAME" } } { "i2c.vhd" "" { Text "F:/vhdl/i2c总线/i2c.vhd" 270 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.152 ns) + CELL(0.740 ns) 4.687 ns Mux0~397 3 COMB LC_X12_Y7_N0 2 " "Info: 3: + IC(1.152 ns) + CELL(0.740 ns) = 4.687 ns; Loc. = LC_X12_Y7_N0; Fanout = 2; COMB Node = 'Mux0~397'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.892 ns" { Mux0~396 Mux0~397 } "NODE_NAME" } } { "i2c.vhd" "" { Text "F:/vhdl/i2c总线/i2c.vhd" 270 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.769 ns) + CELL(0.511 ns) 5.967 ns Mux85~1068 4 COMB LC_X12_Y7_N4 1 " "Info: 4: + IC(0.769 ns) + CELL(0.511 ns) = 5.967 ns; Loc. = LC_X12_Y7_N4; Fanout = 1; COMB Node = 'Mux85~1068'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.280 ns" { Mux0~397 Mux85~1068 } "NODE_NAME" } } { "i2c.vhd" "" { Text "F:/vhdl/i2c总线/i2c.vhd" 160 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.142 ns) + CELL(0.740 ns) 7.849 ns Mux85~1069 5 COMB LC_X13_Y7_N4 1 " "Info: 5: + IC(1.142 ns) + CELL(0.740 ns) = 7.849 ns; Loc. = LC_X13_Y7_N4; Fanout = 1; COMB Node = 'Mux85~1069'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.882 ns" { Mux85~1068 Mux85~1069 } "NODE_NAME" } } { "i2c.vhd" "" { Text "F:/vhdl/i2c总线/i2c.vhd" 160 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.767 ns) + CELL(0.511 ns) 9.127 ns Mux85~1070 6 COMB LC_X13_Y7_N0 1 " "Info: 6: + IC(0.767 ns) + CELL(0.511 ns) = 9.127 ns; Loc. = LC_X13_Y7_N0; Fanout = 1; COMB Node = 'Mux85~1070'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.278 ns" { Mux85~1069 Mux85~1070 } "NODE_NAME" } } { "i2c.vhd" "" { Text "F:/vhdl/i2c总线/i2c.vhd" 160 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.772 ns) + CELL(0.804 ns) 10.703 ns sda_buf 7 REG LC_X13_Y7_N8 21 " "Info: 7: + IC(0.772 ns) + CELL(0.804 ns) = 10.703 ns; Loc. = LC_X13_Y7_N8; Fanout = 21; REG Node = 'sda_buf'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.576 ns" { Mux85~1070 sda_buf } "NODE_NAME" } } { "i2c.vhd" "" { Text "F:/vhdl/i2c总线/i2c.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.817 ns ( 35.66 % ) " "Info: Total cell delay = 3.817 ns ( 35.66 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.886 ns ( 64.34 % ) " "Info: Total interconnect delay = 6.886 ns ( 64.34 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "10.703 ns" { inner_state[2] Mux0~396 Mux0~397 Mux85~1068 Mux85~1069 Mux85~1070 sda_buf } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "10.703 ns" { inner_state[2] Mux0~396 Mux0~397 Mux85~1068 Mux85~1069 Mux85~1070 sda_buf } { 0.000ns 2.284ns 1.152ns 0.769ns 1.142ns 0.767ns 0.772ns } { 0.000ns 0.511ns 0.740ns 0.511ns 0.740ns 0.511ns 0.804ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.344 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 7.344 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 69 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 69; CLK Node = 'clk'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "i2c.vhd" "" { Text "F:/vhdl/i2c总线/i2c.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.294 ns) + CELL(0.918 ns) 7.344 ns sda_buf 2 REG LC_X13_Y7_N8 21 " "Info: 2: + IC(5.294 ns) + CELL(0.918 ns) = 7.344 ns; Loc. = LC_X13_Y7_N8; Fanout = 21; REG Node = 'sda_buf'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.212 ns" { clk sda_buf } "NODE_NAME" } } { "i2c.vhd" "" { Text "F:/vhdl/i2c总线/i2c.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns ( 27.91 % ) " "Info: Total cell delay = 2.050 ns ( 27.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.294 ns ( 72.09 % ) " "Info: Total interconnect delay = 5.294 ns ( 72.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.344 ns" { clk sda_buf } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.344 ns" { clk clk~combout sda_buf } { 0.000ns 0.000ns 5.294ns } { 0.000ns 1.132ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.344 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 7.344 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 69 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 69; CLK Node = 'clk'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "i2c.vhd" "" { Text "F:/vhdl/i2c总线/i2c.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.294 ns) + CELL(0.918 ns) 7.344 ns inner_state\[2\] 2 REG LC_X11_Y5_N7 25 " "Info: 2: + IC(5.294 ns) + CELL(0.918 ns) = 7.344 ns; Loc. = LC_X11_Y5_N7; Fanout = 25; REG Node = 'inner_state\[2\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.212 ns" { clk inner_state[2] } "NODE_NAME" } } { "i2c.vhd" "" { Text "F:/vhdl/i2c总线/i2c.vhd" 148 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns ( 27.91 % ) " "Info: Total cell delay = 2.050 ns ( 27.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.294 ns ( 72.09 % ) " "Info: Total interconnect delay = 5.294 ns ( 72.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.344 ns" { clk inner_state[2] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.344 ns" { clk clk~combout inner_state[2] } { 0.000ns 0.000ns 5.294ns } { 0.000ns 1.132ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.344 ns" { clk sda_buf } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.344 ns" { clk clk~combout sda_buf } { 0.000ns 0.000ns 5.294ns } { 0.000ns 1.132ns 0.918ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.344 ns" { clk inner_state[2] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.344 ns" { clk clk~combout inner_state[2] } { 0.000ns 0.000ns 5.294ns } { 0.000ns 1.132ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "i2c.vhd" "" { Text "F:/vhdl/i2c总线/i2c.vhd" 148 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "i2c.vhd" "" { Text "F:/vhdl/i2c总线/i2c.vhd" 32 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "10.703 ns" { inner_state[2] Mux0~396 Mux0~397 Mux85~1068 Mux85~1069 Mux85~1070 sda_buf } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "10.703 ns" { inner_state[2] Mux0~396 Mux0~397 Mux85~1068 Mux85~1069 Mux85~1070 sda_buf } { 0.000ns 2.284ns 1.152ns 0.769ns 1.142ns 0.767ns 0.772ns } { 0.000ns 0.511ns 0.740ns 0.511ns 0.740ns 0.511ns 0.804ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.344 ns" { clk sda_buf } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.344 ns" { clk clk~combout sda_buf } { 0.000ns 0.000ns 5.294ns } { 0.000ns 1.132ns 0.918ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.344 ns" { clk inner_state[2] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.344 ns" { clk clk~combout inner_state[2] } { 0.000ns 0.000ns 5.294ns } { 0.000ns 1.132ns 0.918ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "sda_buf sda clk 4.362 ns register " "Info: tsu for register \"sda_buf\" (data pin = \"sda\", clock pin = \"clk\") is 4.362 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.373 ns + Longest pin register " "Info: + Longest pin to register delay is 11.373 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sda 1 PIN PIN_78 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_78; Fanout = 1; PIN Node = 'sda'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { sda } "NODE_NAME" } } { "i2c.vhd" "" { Text "F:/vhdl/i2c总线/i2c.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns sda~1 2 COMB IOC_X17_Y3_N2 5 " "Info: 2: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = IOC_X17_Y3_N2; Fanout = 5; COMB Node = 'sda~1'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.132 ns" { sda sda~1 } "NODE_NAME" } } { "i2c.vhd" "" { Text "F:/vhdl/i2c总线/i2c.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.702 ns) + CELL(0.200 ns) 4.034 ns sda_buf~88 3 COMB LC_X12_Y7_N5 4 " "Info: 3: + IC(2.702 ns) + CELL(0.200 ns) = 4.034 ns; Loc. = LC_X12_Y7_N5; Fanout = 4; COMB Node = 'sda_buf~88'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.902 ns" { sda~1 sda_buf~88 } "NODE_NAME" } } { "i2c.vhd" "" { Text "F:/vhdl/i2c总线/i2c.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.964 ns) + CELL(0.511 ns) 6.509 ns Mux41~95 4 COMB LC_X12_Y6_N9 1 " "Info: 4: + IC(1.964 ns) + CELL(0.511 ns) = 6.509 ns; Loc. = LC_X12_Y6_N9; Fanout = 1; COMB Node = 'Mux41~95'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.475 ns" { sda_buf~88 Mux41~95 } "NODE_NAME" } } { "i2c.vhd" "" { Text "F:/vhdl/i2c总线/i2c.vhd" 649 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.733 ns) + CELL(0.200 ns) 7.442 ns Mux85~1073 5 COMB LC_X12_Y6_N0 1 " "Info: 5: + IC(0.733 ns) + CELL(0.200 ns) = 7.442 ns; Loc. = LC_X12_Y6_N0; Fanout = 1; COMB Node = 'Mux85~1073'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.933 ns" { Mux41~95 Mux85~1073 } "NODE_NAME" } } { "i2c.vhd" "" { Text "F:/vhdl/i2c总线/i2c.vhd" 160 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.944 ns) + CELL(0.200 ns) 9.586 ns Mux85~1074 6 COMB LC_X13_Y7_N9 1 " "Info: 6: + IC(1.944 ns) + CELL(0.200 ns) = 9.586 ns; Loc. = LC_X13_Y7_N9; Fanout = 1; COMB Node = 'Mux85~1074'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.144 ns" { Mux85~1073 Mux85~1074 } "NODE_NAME" } } { "i2c.vhd" "" { Text "F:/vhdl/i2c总线/i2c.vhd" 160 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.726 ns) + CELL(1.061 ns) 11.373 ns sda_buf 7 REG LC_X13_Y7_N8 21 " "Info: 7: + IC(0.726 ns) + CELL(1.061 ns) = 11.373 ns; Loc. = LC_X13_Y7_N8; Fanout = 21; REG Node = 'sda_buf'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.787 ns" { Mux85~1074 sda_buf } "NODE_NAME" } } { "i2c.vhd" "" { Text "F:/vhdl/i2c总线/i2c.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.304 ns ( 29.05 % ) " "Info: Total cell delay = 3.304 ns ( 29.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.069 ns ( 70.95 % ) " "Info: Total interconnect delay = 8.069 ns ( 70.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "11.373 ns" { sda sda~1 sda_buf~88 Mux41~95 Mux85~1073 Mux85~1074 sda_buf } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "11.373 ns" { sda sda~1 sda_buf~88 Mux41~95 Mux85~1073 Mux85~1074 sda_buf } { 0.000ns 0.000ns 2.702ns 1.964ns 0.733ns 1.944ns 0.726ns } { 0.000ns 1.132ns 0.200ns 0.511ns 0.200ns 0.200ns 1.061ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "i2c.vhd" "" { Text "F:/vhdl/i2c总线/i2c.vhd" 32 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.344 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 7.344 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 69 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 69; CLK Node = 'clk'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "i2c.vhd" "" { Text "F:/vhdl/i2c总线/i2c.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.294 ns) + CELL(0.918 ns) 7.344 ns sda_buf 2 REG LC_X13_Y7_N8 21 " "Info: 2: + IC(5.294 ns) + CELL(0.918 ns) = 7.344 ns; Loc. = LC_X13_Y7_N8; Fanout = 21; REG Node = 'sda_buf'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.212 ns" { clk sda_buf } "NODE_NAME" } } { "i2c.vhd" "" { Text "F:/vhdl/i2c总线/i2c.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns ( 27.91 % ) " "Info: Total cell delay = 2.050 ns ( 27.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.294 ns ( 72.09 % ) " "Info: Total interconnect delay = 5.294 ns ( 72.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.344 ns" { clk sda_buf } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.344 ns" { clk clk~combout sda_buf } { 0.000ns 0.000ns 5.294ns } { 0.000ns 1.132ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "11.373 ns" { sda sda~1 sda_buf~88 Mux41~95 Mux85~1073 Mux85~1074 sda_buf } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "11.373 ns" { sda sda~1 sda_buf~88 Mux41~95 Mux85~1073 Mux85~1074 sda_buf } { 0.000ns 0.000ns 2.702ns 1.964ns 0.733ns 1.944ns 0.726ns } { 0.000ns 1.132ns 0.200ns 0.511ns 0.200ns 0.200ns 1.061ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.344 ns" { clk sda_buf } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.344 ns" { clk clk~combout sda_buf } { 0.000ns 0.000ns 5.294ns } { 0.000ns 1.132ns 0.918ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}