prev_cmp_i2c.map.qmsg

FPGA使用I2C总线

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 178 06/25/2007 Service Pack 1 SJ Full Version " "Info: Version 7.1 Build 178 06/25/2007 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 09 17:43:09 2007 " "Info: Processing started: Tue Oct 09 17:43:09 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off i2c -c i2c " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off i2c -c i2c" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "i2c.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file i2c.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 i2c-translated " "Info: Found design unit 1: i2c-translated" {  } { { "i2c.vhd" "" { Text "F:/vhdl/i2c总线/i2c.vhd" 27 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 i2c " "Info: Found entity 1: i2c" {  } { { "i2c.vhd" "" { Text "F:/vhdl/i2c总线/i2c.vhd" 13 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "i2c " "Info: Elaborating entity \"i2c\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "addr i2c.vhd(145) " "Warning (10631): VHDL Process Statement warning at i2c.vhd(145): inferring latch(es) for signal or variable \"addr\", which holds its previous value in one or more paths through the process" {  } { { "i2c.vhd" "" { Text "F:/vhdl/i2c总线/i2c.vhd" 145 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "addr\[0\] i2c.vhd(145) " "Info (10041): Inferred latch for \"addr\[0\]\" at i2c.vhd(145)" {  } { { "i2c.vhd" "" { Text "F:/vhdl/i2c总线/i2c.vhd" 145 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "addr\[1\] i2c.vhd(145) " "Info (10041): Inferred latch for \"addr\[1\]\" at i2c.vhd(145)" {  } { { "i2c.vhd" "" { Text "F:/vhdl/i2c总线/i2c.vhd" 145 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "addr\[2\] i2c.vhd(145) " "Info (10041): Inferred latch for \"addr\[2\]\" at i2c.vhd(145)" {  } { { "i2c.vhd" "" { Text "F:/vhdl/i2c总线/i2c.vhd" 145 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "addr\[3\] i2c.vhd(145) " "Info (10041): Inferred latch for \"addr\[3\]\" at i2c.vhd(145)" {  } { { "i2c.vhd" "" { Text "F:/vhdl/i2c总线/i2c.vhd" 145 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "addr\[4\] i2c.vhd(145) " "Info (10041): Inferred latch for \"addr\[4\]\" at i2c.vhd(145)" {  } { { "i2c.vhd" "" { Text "F:/vhdl/i2c总线/i2c.vhd" 145 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "addr\[5\] i2c.vhd(145) " "Info (10041): Inferred latch for \"addr\[5\]\" at i2c.vhd(145)" {  } { { "i2c.vhd" "" { Text "F:/vhdl/i2c总线/i2c.vhd" 145 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "addr\[6\] i2c.vhd(145) " "Info (10041): Inferred latch for \"addr\[6\]\" at i2c.vhd(145)" {  } { { "i2c.vhd" "" { Text "F:/vhdl/i2c总线/i2c.vhd" 145 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "addr\[7\] i2c.vhd(145) " "Info (10041): Inferred latch for \"addr\[7\]\" at i2c.vhd(145)" {  } { { "i2c.vhd" "" { Text "F:/vhdl/i2c总线/i2c.vhd" 145 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "writeData_reg\[4\] writeData_reg\[7\] " "Info: Duplicate register \"writeData_reg\[4\]\" merged to single register \"writeData_reg\[7\]\"" {  } { { "i2c.vhd" "" { Text "F:/vhdl/i2c总线/i2c.vhd" 148 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "writeData_reg\[5\] writeData_reg\[7\] " "Info: Duplicate register \"writeData_reg\[5\]\" merged to single register \"writeData_reg\[7\]\"" {  } { { "i2c.vhd" "" { Text "F:/vhdl/i2c总线/i2c.vhd" 148 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "writeData_reg\[6\] writeData_reg\[7\] " "Info: Duplicate register \"writeData_reg\[6\]\" merged to single register \"writeData_reg\[7\]\"" {  } { { "i2c.vhd" "" { Text "F:/vhdl/i2c总线/i2c.vhd" 148 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "writeData_reg\[7\] data_in GND " "Warning: Reduced register \"writeData_reg\[7\]\" with stuck data_in port to stuck value GND" {  } { { "i2c.vhd" "" { Text "F:/vhdl/i2c总线/i2c.vhd" 148 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "clk_div\[0\] cnt_scan\[0\] " "Info: Duplicate register \"clk_div\[0\]\" merged to single register \"cnt_scan\[0\]\"" {  } { { "i2c.vhd" "" { Text "F:/vhdl/i2c总线/i2c.vhd" 101 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "clk_div\[1\] cnt_scan\[1\] " "Info: Duplicate register \"clk_div\[1\]\" merged to single register \"cnt_scan\[1\]\"" {  } { { "i2c.vhd" "" { Text "F:/vhdl/i2c总线/i2c.vhd" 101 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0 "" 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "lowbit GND " "Warning: Pin \"lowbit\" stuck at GND" {  } { { "i2c.vhd" "" { Text "F:/vhdl/i2c总线/i2c.vhd" 22 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "seg_data\[0\] VCC " "Warning: Pin \"seg_data\[0\]\" stuck at VCC" {  } { { "i2c.vhd" "" { Text "F:/vhdl/i2c总线/i2c.vhd" 24 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "i2c.vhd" "" { Text "F:/vhdl/i2c总线/i2c.vhd" 148 -1 0 } } { "i2c.vhd" "" { Text "F:/vhdl/i2c总线/i2c.vhd" 770 -1 0 } } { "i2c.vhd" "" { Text "F:/vhdl/i2c总线/i2c.vhd" 148 -1 0 } } { "i2c.vhd" "" { Text "F:/vhdl/i2c总线/i2c.vhd" 148 -1 0 } } { "i2c.vhd" "" { Text "F:/vhdl/i2c总线/i2c.vhd" 32 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "275 " "Info: Implemented 275 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "8 " "Info: Implemented 8 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "12 " "Info: Implemented 12 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_BIDIRS" "1 " "Info: Implemented 1 bidirectional pins" {  } {  } 0 0 "Implemented %1!d! bidirectional pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "254 " "Info: Implemented 254 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "153 " "Info: Allocated 153 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 09 17:43:29 2007 " "Info: Processing ended: Tue Oct 09 17:43:29 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:20 " "Info: Elapsed time: 00:00:20" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}