i2c.map.eqn

FPGA使用I2C总线

--A1L472 is rtl~2794
--operation mode is normal

A1L472 = inner_state[3] & phase3 & (!inner_state[0]);


--A1L631 is main_state[0]~1743
--operation mode is normal

A1L631 = inner_state[2] # !A1L472 # !i2c_state[0] # !inner_state[1];


--A1L731 is main_state[0]~1744
--operation mode is normal

A1L731 = sda_buf # !A1L641 # !phase1 # !inner_state[3];


--A1L831 is main_state[0]~1745
--operation mode is normal

A1L831 = A1L841 # i2c_state[1] & A1L631 # !i2c_state[1] & (A1L731);


--cnt_delay[18] is cnt_delay[18]
--operation mode is normal

cnt_delay[18]_lut_out = A1L41 & A1L442;
cnt_delay[18] = DFFEAS(cnt_delay[18]_lut_out, clk, rst, , start_delaycnt, , , , );


--cnt_delay[13] is cnt_delay[13]
--operation mode is normal

cnt_delay[13]_lut_out = A1L61 & A1L442;
cnt_delay[13] = DFFEAS(cnt_delay[13]_lut_out, clk, rst, , start_delaycnt, , , , );


--cnt_delay[12] is cnt_delay[12]
--operation mode is normal

cnt_delay[12]_lut_out = A1L81 & A1L442;
cnt_delay[12] = DFFEAS(cnt_delay[12]_lut_out, clk, rst, , start_delaycnt, , , , );


--cnt_delay[10] is cnt_delay[10]
--operation mode is normal

cnt_delay[10]_lut_out = A1L02 & A1L442;
cnt_delay[10] = DFFEAS(cnt_delay[10]_lut_out, clk, rst, , start_delaycnt, , , , );


--A1L052 is reduce_nor~202
--operation mode is normal

A1L052 = !cnt_delay[10] # !cnt_delay[12] # !cnt_delay[13] # !cnt_delay[18];


--cnt_delay[17] is cnt_delay[17]
--operation mode is normal

cnt_delay[17]_lut_out = A1L22;
cnt_delay[17] = DFFEAS(cnt_delay[17]_lut_out, clk, rst, , start_delaycnt, , , , );


--cnt_delay[16] is cnt_delay[16]
--operation mode is normal

cnt_delay[16]_lut_out = A1L42;
cnt_delay[16] = DFFEAS(cnt_delay[16]_lut_out, clk, rst, , start_delaycnt, , , , );


--cnt_delay[15] is cnt_delay[15]
--operation mode is normal

cnt_delay[15]_lut_out = A1L62;
cnt_delay[15] = DFFEAS(cnt_delay[15]_lut_out, clk, rst, , start_delaycnt, , , , );


--cnt_delay[14] is cnt_delay[14]
--operation mode is normal

cnt_delay[14]_lut_out = A1L82;
cnt_delay[14] = DFFEAS(cnt_delay[14]_lut_out, clk, rst, , start_delaycnt, , , , );


--A1L222 is process2~149
--operation mode is normal

A1L222 = !cnt_delay[17] & !cnt_delay[16] & !cnt_delay[15] & !cnt_delay[14];


--cnt_delay[11] is cnt_delay[11]
--operation mode is normal

cnt_delay[11]_lut_out = A1L03;
cnt_delay[11] = DFFEAS(cnt_delay[11]_lut_out, clk, rst, , start_delaycnt, , , , );


--cnt_delay[9] is cnt_delay[9]
--operation mode is normal

cnt_delay[9]_lut_out = A1L23;
cnt_delay[9] = DFFEAS(cnt_delay[9]_lut_out, clk, rst, , start_delaycnt, , , , );


--cnt_delay[7] is cnt_delay[7]
--operation mode is normal

cnt_delay[7]_lut_out = A1L43;
cnt_delay[7] = DFFEAS(cnt_delay[7]_lut_out, clk, rst, , start_delaycnt, , , , );


--cnt_delay[6] is cnt_delay[6]
--operation mode is normal

cnt_delay[6]_lut_out = A1L63;
cnt_delay[6] = DFFEAS(cnt_delay[6]_lut_out, clk, rst, , start_delaycnt, , , , );


--A1L322 is process2~150
--operation mode is normal

A1L322 = !cnt_delay[11] & !cnt_delay[9] & !cnt_delay[7] & !cnt_delay[6];


--cnt_delay[5] is cnt_delay[5]
--operation mode is normal

cnt_delay[5]_lut_out = A1L83;
cnt_delay[5] = DFFEAS(cnt_delay[5]_lut_out, clk, rst, , start_delaycnt, , , , );


--cnt_delay[4] is cnt_delay[4]
--operation mode is normal

cnt_delay[4]_lut_out = A1L04;
cnt_delay[4] = DFFEAS(cnt_delay[4]_lut_out, clk, rst, , start_delaycnt, , , , );


--cnt_delay[3] is cnt_delay[3]
--operation mode is normal

cnt_delay[3]_lut_out = A1L24;
cnt_delay[3] = DFFEAS(cnt_delay[3]_lut_out, clk, rst, , start_delaycnt, , , , );


--cnt_delay[2] is cnt_delay[2]
--operation mode is normal

cnt_delay[2]_lut_out = A1L44;
cnt_delay[2] = DFFEAS(cnt_delay[2]_lut_out, clk, rst, , start_delaycnt, , , , );


--A1L422 is process2~151
--operation mode is normal

A1L422 = !cnt_delay[5] & !cnt_delay[4] & !cnt_delay[3] & !cnt_delay[2];


--cnt_delay[1] is cnt_delay[1]
--operation mode is normal

cnt_delay[1]_lut_out = A1L64;
cnt_delay[1] = DFFEAS(cnt_delay[1]_lut_out, clk, rst, , start_delaycnt, , , , );


--cnt_delay[0] is cnt_delay[0]
--operation mode is normal

cnt_delay[0]_lut_out = A1L84 & A1L442;
cnt_delay[0] = DFFEAS(cnt_delay[0]_lut_out, clk, rst, , start_delaycnt, , , , );


--A1L522 is process2~152
--operation mode is normal

A1L522 = !cnt_delay[1] & !cnt_delay[0];


--A1L622 is process2~153
--operation mode is normal

A1L622 = A1L222 & A1L322 & A1L422 & A1L522;


--cnt_delay[8] is cnt_delay[8]
--operation mode is normal

cnt_delay[8]_lut_out = A1L05 & A1L442;
cnt_delay[8] = DFFEAS(cnt_delay[8]_lut_out, clk, rst, , start_delaycnt, , , , );


--cnt_delay[19] is cnt_delay[19]
--operation mode is normal

cnt_delay[19]_lut_out = A1L25 & A1L442;
cnt_delay[19] = DFFEAS(cnt_delay[19]_lut_out, clk, rst, , start_delaycnt, , , , );


--A1L442 is reduce_nor~5
--operation mode is normal

A1L442 = A1L052 # !cnt_delay[19] # !cnt_delay[8] # !A1L622;


--A1L931 is main_state[0]~1746
--operation mode is normal

A1L931 = wr_input & rd_input;


--A1L041 is main_state[0]~1747
--operation mode is normal

A1L041 = main_state[1] & A1L831 # !main_state[1] & (A1L442 # A1L931);


--A1L141 is main_state[0]~1748
--operation mode is normal

A1L141 = A1L531 & (A1L741 # A1L041 & !main_state[0]) # !A1L531 & (A1L041 & !main_state[0]);


--A1L152 is reduce_nor~203
--operation mode is normal

A1L152 = cnt_scan[1] & clk_div[6] & (!clk_div[4]);


--A1L1 is add~549
--operation mode is arithmetic

A1L1 = !clk_div[0];

--A1L2 is add~551
--operation mode is arithmetic

A1L2 = CARRY(clk_div[0]);


--A1L252 is reduce_nor~204
--operation mode is normal

A1L252 = !clk_div[0] & !clk_div[7] & !clk_div[2] & !clk_div[5];


--A1L242 is reduce_nor~1
--operation mode is normal

A1L242 = !A1L252 # !A1L022 # !clk_div[3];


--A1L941 is Mux~11431
--operation mode is normal

A1L941 = inner_state[3] & phase3 & A1L641;


--A1L051 is Mux~11432
--operation mode is normal

A1L051 = i2c_state[2] # i2c_state[1] # !A1L941;


--A1L151 is Mux~11433
--operation mode is normal

A1L151 = i2c_state[0] & (main_state[1] & (main_state[0] # A1L051) # !main_state[1] & main_state[0] & A1L051);


--A1L251 is Mux~11434
--operation mode is normal

A1L251 = A1L941 & (!i2c_state[0] & !i2c_state[1]);


--A1L351 is Mux~11436
--operation mode is normal

A1L351 = i2c_state[0] & A1L941 & (!i2c_state[1]);


--A1L451 is Mux~11437
--operation mode is normal

A1L451 = i2c_state[2] & !main_state[0] & !i2c_state[0] & main_state[1] # !i2c_state[2] & main_state[0] & i2c_state[0] & !main_state[1];


--A1L572 is rtl~2795
--operation mode is normal

A1L572 = inner_state[1] & inner_state[2] & phase3 & inner_state[0];


--A1L672 is rtl~2796
--operation mode is normal

A1L672 = phase3 & inner_state[0] & !inner_state[1] & !inner_state[2];


--A1L772 is rtl~2797
--operation mode is normal

A1L772 = A1L572 # inner_state[3] & (i2c_state[1] # !A1L672);


--A1L551 is Mux~11439
--operation mode is normal

A1L551 = A1L572 # inner_state[3] & (!A1L672);


--A1L072 is rtl~1
--operation mode is normal

A1L072 = main_state[0] & A1L772;


--A1L872 is rtl~2798
--operation mode is normal

A1L872 = !i2c_state[2] & !main_state[1] & (!i2c_state[1] # !i2c_state[0]);


--A1L972 is rtl~2799
--operation mode is normal

A1L972 = !i2c_state[0] & !i2c_state[1] # !main_state[1];


--A1L082 is rtl~2800
--operation mode is normal

A1L082 = A1L872 # !main_state[0] & (A1L372 # A1L972);


--A1L172 is rtl~10
--operation mode is normal

A1L172 = inner_state[2] $ phase3;


--A1L272 is rtl~13
--operation mode is normal

A1L272 = A1L621 & main_state[0];


--A1L182 is rtl~2801
--operation mode is normal

A1L182 = inner_state[1] & inner_state[0] & (!inner_state[3]);


--A1L282 is rtl~2802
--operation mode is normal

A1L282 = i2c_state[1] & (!inner_state[2]);


--A1L651 is Mux~11440
--operation mode is normal

A1L651 = phase3 & inner_state[0];


--A1L382 is rtl~2803
--operation mode is normal

A1L382 = inner_state[3] & (inner_state[1] # A1L282 & A1L651) # !inner_state[3] & (inner_state[1] $ A1L651);


--A1L751 is Mux~11441
--operation mode is normal

A1L751 = inner_state[1] $ (!inner_state[3] & phase3 & inner_state[0]);


--A1L482 is rtl~2804
--operation mode is normal

A1L482 = i2c_state[1] & (!inner_state[2] & !phase1);


--A1L582 is rtl~2805
--operation mode is normal

A1L582 = inner_state[3] & (inner_state[1] # A1L482 & A1L651) # !inner_state[3] & (inner_state[1] $ A1L651);


--A1L682 is rtl~2806
--operation mode is normal

A1L682 = main_state[0] & A1L582;


--A1L851 is Mux~11442
--operation mode is normal

A1L851 = !inner_state[1] & !inner_state[2];


--A1L951 is Mux~11443
--operation mode is normal

A1L951 = inner_state[0] & (inner_state[3] & !A1L851 # !phase3) # !inner_state[0] & phase3 & (inner_state[3] $ !A1L851);


--A1L061 is Mux~11444
--operation mode is normal

A1L061 = phase3 & inner_state[3] & (inner_state[0] # A1L851) # !phase3 & (inner_state[0]);


--A1L161 is Mux~11445
--operation mode is normal

A1L161 = phase3 & (!inner_state[0]);


--link is link
--operation mode is normal

link_lut_out = i2c_state[2] & (A1L412) # !i2c_state[2] & A1L292;
link = DFFEAS(link_lut_out, clk, rst, , A1L082, A1L692, , , !main_state[1]);


--A1L261 is Mux~11446
--operation mode is normal

A1L261 = inner_state[1] # inner_state[2] # link;


--A1L361 is Mux~11447
--operation mode is normal

A1L361 = A1L061 # A1L161 & A1L261 & !inner_state[3];


--A1L461 is Mux~11448
--operation mode is normal

A1L461 = i2c_state[0] & A1L951 # !i2c_state[0] & (A1L361);


--A1L561 is Mux~11449
--operation mode is normal

A1L561 = !main_state[0] & (i2c_state[0] & (!i2c_state[2]) # !i2c_state[0] & !i2c_state[1]);


--A1L661 is Mux~11450
--operation mode is normal

A1L661 = main_state[1] & (A1L561 & A1L461 # !A1L561 & (inner_state[0]));


--A1L761 is Mux~11451
--operation mode is normal

A1L761 = i2c_state[2] & main_state[0] & inner_state[0];


--A1L861 is Mux~11452
--operation mode is normal

A1L861 = phase3 & (inner_state[3] & (inner_state[0] $ A1L312) # !inner_state[3] & !inner_state[0] & !A1L312) # !phase3 & (inner_state[0]);


--A1L961 is Mux~11453
--operation mode is normal

A1L961 = phase3 & (inner_state[3] $ (!inner_state[0] & !A1L851)) # !phase3 & (inner_state[0]);


--A1L071 is Mux~11454
--operation mode is normal

A1L071 = i2c_state[1] & (i2c_state[0]) # !i2c_state[1] & (i2c_state[0] & A1L961 # !i2c_state[0] & (A1L361));


--A1L171 is Mux~11455
--operation mode is normal

A1L171 = i2c_state[1] & (A1L071 & (inner_state[0]) # !A1L071 & A1L861) # !i2c_state[1] & (A1L071);


--A1L3 is add~554
--operation mode is arithmetic

A1L3_carry_eqn = A1L9;
A1L3 = clk_div[3] $ (A1L3_carry_eqn);

--A1L4 is add~556
--operation mode is arithmetic

A1L4 = CARRY(!A1L9 # !clk_div[3]);


--A1L5 is add~559
--operation mode is arithmetic

A1L5_carry_eqn = A1L11;
A1L5 = clk_div[5] $ (A1L5_carry_eqn);

--A1L6 is add~561
--operation mode is arithmetic

A1L6 = CARRY(!A1L11 # !clk_div[5]);


--A1L7 is add~564
--operation mode is normal

A1L7_carry_eqn = A1L31;
A1L7 = clk_div[7] $ (A1L7_carry_eqn);


--A1L8 is add~569
--operation mode is arithmetic

A1L8_carry_eqn = A1L45;
A1L8 = clk_div[2] $ (!A1L8_carry_eqn);

--A1L9 is add~571
--operation mode is arithmetic

A1L9 = CARRY(clk_div[2] & (!A1L45));


--A1L01 is add~574
--operation mode is arithmetic

A1L01_carry_eqn = A1L4;
A1L01 = clk_div[4] $ (!A1L01_carry_eqn);

--A1L11 is add~576
--operation mode is arithmetic

A1L11 = CARRY(clk_div[4] & (!A1L4));


--A1L21 is add~579
--operation mode is arithmetic

A1L21_carry_eqn = A1L6;
A1L21 = clk_div[6] $ (!A1L21_carry_eqn);

--A1L31 is add~581
--operation mode is arithmetic

A1L31 = CARRY(clk_div[6] & (!A1L6));


--A1L342 is reduce_nor~3
--operation mode is normal

A1L342 = !A1L252 # !A1L152 # !clk_div[3];


--A1L271 is Mux~11457
--operation mode is normal

A1L271 = phase3 & inner_state[1] & inner_state[0] # !phase3 & (!sda_buf);


--A1L371 is Mux~11458
--operation mode is normal

A1L371 = inner_state[0] & (!inner_state[1]);


--A1L471 is Mux~11459
--operation mode is normal

A1L471 = phase0 & (A1L371 & A1L203 # !A1L371 & (!sda_buf)) # !phase0 & (!sda_buf);


--A1L571 is Mux~11460
--operation mode is normal

A1L571 = inner_state[1] # !phase1;


--A1L671 is Mux~11461
--operation mode is normal

A1L671 = !sda_buf & (inner_state[0] & (!phase3) # !inner_state[0] & A1L571);


--A1L771 is Mux~11462
--operation mode is normal

A1L771 = A1L671 # A1L161 & (inner_state[1] # link);


--A1L871 is Mux~11463
--operation mode is normal

A1L871 = inner_state[2] & (inner_state[3]) # !inner_state[2] & (inner_state[3] & A1L471 # !inner_state[3] & (A1L771));


--A1L971 is Mux~11464
--operation mode is normal

A1L971 = inner_state[2] & (A1L871 & (!sda_buf) # !A1L871 & A1L271) # !inner_state[2] & (A1L871);


--A1L103 is sda_buf~92
--operation mode is normal

A1L103 = phase0 & A1L203 # !phase0 & (!sda_buf);


--A1L081 is Mux~11465
--operation mode is normal

A1L081 = A1L641 & (phase3 # A1L103) # !A1L641 & (!sda_buf);


--A1L181 is Mux~11466
--operation mode is normal

A1L181 = !inner_state[1] & !inner_state[2] & !inner_state[0] # !phase3;


--A1L281 is Mux~11467
--operation mode is normal

A1L281 = inner_state[2] & (A1L161 # A1L181 & !sda_buf) # !inner_state[2] & (A1L181 & !sda_buf);


--A1L381 is Mux~11468
--operation mode is normal

A1L381 = inner_state[3] & A1L081 # !inner_state[3] & (A1L281);


--A1L481 is Mux~11469
--operation mode is normal

A1L481 = A1L641 & A1L103 & (!phase3) # !A1L641 & (!sda_buf);