i2c.map.eqn

FPGA使用I2C总线

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--scl_xhdl1 is scl_xhdl1
--operation mode is normal

scl_xhdl1_lut_out = !A1L341 & (main_state[1] $ !main_state[0] # !phase0);
scl_xhdl1 = DFFEAS(scl_xhdl1_lut_out, clk, rst, , , , , , );


--en_xhdl3[0] is en_xhdl3[0]
--operation mode is normal

en_xhdl3[0]_lut_out = !en_xhdl3[0];
en_xhdl3[0] = DFFEAS(en_xhdl3[0]_lut_out, clk, rst, , A1L842, , , , );


--en_xhdl3[1] is en_xhdl3[1]
--operation mode is normal

en_xhdl3[1]_lut_out = !en_xhdl3[1];
en_xhdl3[1] = DFFEAS(en_xhdl3[1]_lut_out, clk, rst, , A1L842, , , , );


--readData_reg[3] is readData_reg[3]
--operation mode is normal

readData_reg[3]_lut_out = readData_reg[2];
readData_reg[3] = DFFEAS(readData_reg[3]_lut_out, clk, rst, , A1L432, , , , );


--writeData_reg[3] is writeData_reg[3]
--operation mode is normal

writeData_reg[3]_lut_out = data_in[3];
writeData_reg[3] = DFFEAS(writeData_reg[3]_lut_out, clk, rst, , A1L541, , , , );


--A1L513 is seg_data_buf[3]~535
--operation mode is normal

A1L513 = en_xhdl3[0] & readData_reg[3] & en_xhdl3[1] # !en_xhdl3[0] & (!en_xhdl3[1] & writeData_reg[3]);


--readData_reg[2] is readData_reg[2]
--operation mode is normal

readData_reg[2]_lut_out = readData_reg[1];
readData_reg[2] = DFFEAS(readData_reg[2]_lut_out, clk, rst, , A1L432, , , , );


--writeData_reg[2] is writeData_reg[2]
--operation mode is normal

writeData_reg[2]_lut_out = !data_in[2];
writeData_reg[2] = DFFEAS(writeData_reg[2]_lut_out, clk, rst, , A1L541, , , , );


--A1L413 is seg_data_buf[2]~536
--operation mode is normal

A1L413 = en_xhdl3[0] & readData_reg[2] & en_xhdl3[1] # !en_xhdl3[0] & (!en_xhdl3[1] & !writeData_reg[2]);


--readData_reg[1] is readData_reg[1]
--operation mode is normal

readData_reg[1]_lut_out = readData_reg[0];
readData_reg[1] = DFFEAS(readData_reg[1]_lut_out, clk, rst, , A1L432, , , , );


--writeData_reg[1] is writeData_reg[1]
--operation mode is normal

writeData_reg[1]_lut_out = data_in[1];
writeData_reg[1] = DFFEAS(writeData_reg[1]_lut_out, clk, rst, , A1L541, , , , );


--A1L313 is seg_data_buf[1]~537
--operation mode is normal

A1L313 = en_xhdl3[0] & readData_reg[1] & en_xhdl3[1] # !en_xhdl3[0] & (!en_xhdl3[1] & writeData_reg[1]);


--readData_reg[0] is readData_reg[0]
--operation mode is normal

readData_reg[0]_lut_out = A1L203;
readData_reg[0] = DFFEAS(readData_reg[0]_lut_out, clk, rst, , A1L432, , , , );


--writeData_reg[0] is writeData_reg[0]
--operation mode is normal

writeData_reg[0]_lut_out = !data_in[0];
writeData_reg[0] = DFFEAS(writeData_reg[0]_lut_out, clk, rst, , A1L541, , , , );


--A1L213 is seg_data_buf[0]~538
--operation mode is normal

A1L213 = en_xhdl3[0] & readData_reg[0] & en_xhdl3[1] # !en_xhdl3[0] & (!en_xhdl3[1] & !writeData_reg[0]);


--A1L352 is reduce_or~2133
--operation mode is normal

A1L352 = A1L213 & (A1L513 # A1L413 $ A1L313) # !A1L213 & (A1L313 # A1L513 $ A1L413);


--readData_reg[7] is readData_reg[7]
--operation mode is normal

readData_reg[7]_lut_out = readData_reg[6];
readData_reg[7] = DFFEAS(readData_reg[7]_lut_out, clk, rst, , A1L432, , , , );


--readData_reg[5] is readData_reg[5]
--operation mode is normal

readData_reg[5]_lut_out = readData_reg[4];
readData_reg[5] = DFFEAS(readData_reg[5]_lut_out, clk, rst, , A1L432, , , , );


--A1L452 is reduce_or~2134
--operation mode is normal

A1L452 = !readData_reg[7] & !readData_reg[5] # !en_xhdl3[1] # !en_xhdl3[0];


--readData_reg[6] is readData_reg[6]
--operation mode is normal

readData_reg[6]_lut_out = readData_reg[5];
readData_reg[6] = DFFEAS(readData_reg[6]_lut_out, clk, rst, , A1L432, , , , );


--readData_reg[4] is readData_reg[4]
--operation mode is normal

readData_reg[4]_lut_out = readData_reg[3];
readData_reg[4] = DFFEAS(readData_reg[4]_lut_out, clk, rst, , A1L432, , , , );


--A1L552 is reduce_or~2135
--operation mode is normal

A1L552 = !readData_reg[6] & !readData_reg[4] # !en_xhdl3[1] # !en_xhdl3[0];


--A1L652 is reduce_or~2136
--operation mode is normal

A1L652 = !A1L552 # !A1L452 # !A1L352;


--A1L752 is reduce_or~2137
--operation mode is normal

A1L752 = A1L413 & A1L213 & (A1L513 $ A1L313) # !A1L413 & !A1L513 & (A1L313 # A1L213);


--A1L852 is reduce_or~2138
--operation mode is normal

A1L852 = A1L752 # !A1L552 # !A1L452;


--A1L952 is reduce_or~2139
--operation mode is normal

A1L952 = A1L313 & !A1L513 & (A1L213) # !A1L313 & (A1L413 & !A1L513 # !A1L413 & (A1L213));


--A1L062 is reduce_or~2140
--operation mode is normal

A1L062 = A1L952 # !A1L552 # !A1L452;


--A1L162 is reduce_or~2141
--operation mode is normal

A1L162 = A1L213 & (A1L413 $ !A1L313) # !A1L213 & (A1L513 & !A1L413 & A1L313 # !A1L513 & A1L413 & !A1L313);


--A1L262 is reduce_or~2142
--operation mode is normal

A1L262 = A1L162 # !A1L552 # !A1L452;


--A1L362 is reduce_or~2143
--operation mode is normal

A1L362 = A1L513 & A1L413 & (A1L313 # !A1L213) # !A1L513 & !A1L413 & A1L313 & !A1L213;


--A1L462 is reduce_or~2144
--operation mode is normal

A1L462 = A1L362 # !A1L552 # !A1L452;


--A1L562 is reduce_or~2145
--operation mode is normal

A1L562 = A1L513 & (A1L213 & (A1L313) # !A1L213 & A1L413) # !A1L513 & A1L413 & (A1L313 $ A1L213);


--A1L662 is reduce_or~2146
--operation mode is normal

A1L662 = A1L562 # !A1L552 # !A1L452;


--A1L762 is reduce_or~2147
--operation mode is normal

A1L762 = A1L513 & A1L213 & (A1L413 $ A1L313) # !A1L513 & !A1L313 & (A1L413 $ A1L213);


--A1L862 is reduce_or~2148
--operation mode is normal

A1L862 = A1L762 # !A1L552 # !A1L452;


--phase2 is phase2
--operation mode is normal

phase2_lut_out = !phase2 & !clk_div[3] & A1L942 & A1L022;
phase2 = DFFEAS(phase2_lut_out, clk, rst, , , , , , );


--main_state[1] is main_state[1]
--operation mode is normal

main_state[1]_lut_out = main_state[1] & (main_state[0] # A1L141) # !main_state[1] & !main_state[0] & !A1L141 & wr_input;
main_state[1] = DFFEAS(main_state[1]_lut_out, clk, rst, , , , , , );


--main_state[0] is main_state[0]
--operation mode is normal

main_state[0]_lut_out = main_state[0] & (main_state[1] # A1L141) # !main_state[0] & !main_state[1] & !A1L141 & !wr_input;
main_state[0] = DFFEAS(main_state[0]_lut_out, clk, rst, , , , , , );


--A1L341 is Mux~11424
--operation mode is normal

A1L341 = scl_xhdl1 & (!main_state[1] & !main_state[0]) # !scl_xhdl1 & (main_state[1] $ !main_state[0] # !phase2);


--phase0 is phase0
--operation mode is normal

phase0_lut_out = !phase0 & !clk_div[3] & A1L942 & A1L152;
phase0 = DFFEAS(phase0_lut_out, clk, rst, , , , , , );


--cnt_scan[1] is cnt_scan[1]
--operation mode is arithmetic

cnt_scan[1]_lut_out = cnt_scan[1] $ clk_div[0];
cnt_scan[1] = DFFEAS(cnt_scan[1]_lut_out, clk, rst, , , , , , );

--A1L78 is cnt_scan[1]~184
--operation mode is arithmetic

A1L78 = CARRY(cnt_scan[1] & clk_div[0]);


--cnt_scan[2] is cnt_scan[2]
--operation mode is arithmetic

cnt_scan[2]_carry_eqn = A1L78;
cnt_scan[2]_lut_out = cnt_scan[2] $ (cnt_scan[2]_carry_eqn);
cnt_scan[2] = DFFEAS(cnt_scan[2]_lut_out, clk, rst, , , , , , );

--A1L98 is cnt_scan[2]~188
--operation mode is arithmetic

A1L98 = CARRY(!A1L78 # !cnt_scan[2]);


--cnt_scan[3] is cnt_scan[3]
--operation mode is arithmetic

cnt_scan[3]_carry_eqn = A1L98;
cnt_scan[3]_lut_out = cnt_scan[3] $ (!cnt_scan[3]_carry_eqn);
cnt_scan[3] = DFFEAS(cnt_scan[3]_lut_out, clk, rst, , , , , , );

--A1L19 is cnt_scan[3]~192
--operation mode is arithmetic

A1L19 = CARRY(cnt_scan[3] & (!A1L98));


--clk_div[0] is clk_div[0]
--operation mode is normal

clk_div[0]_lut_out = A1L1;
clk_div[0] = DFFEAS(clk_div[0]_lut_out, clk, rst, , , , , , );


--A1L542 is reduce_nor~197
--operation mode is normal

A1L542 = !clk_div[0] # !cnt_scan[3] # !cnt_scan[2] # !cnt_scan[1];


--cnt_scan[4] is cnt_scan[4]
--operation mode is arithmetic

cnt_scan[4]_carry_eqn = A1L19;
cnt_scan[4]_lut_out = cnt_scan[4] $ (cnt_scan[4]_carry_eqn);
cnt_scan[4] = DFFEAS(cnt_scan[4]_lut_out, clk, rst, , , , , , );

--A1L39 is cnt_scan[4]~196
--operation mode is arithmetic

A1L39 = CARRY(!A1L19 # !cnt_scan[4]);


--cnt_scan[5] is cnt_scan[5]
--operation mode is arithmetic

cnt_scan[5]_carry_eqn = A1L39;
cnt_scan[5]_lut_out = cnt_scan[5] $ (!cnt_scan[5]_carry_eqn);
cnt_scan[5] = DFFEAS(cnt_scan[5]_lut_out, clk, rst, , , , , , );

--A1L59 is cnt_scan[5]~200
--operation mode is arithmetic

A1L59 = CARRY(cnt_scan[5] & (!A1L39));


--cnt_scan[6] is cnt_scan[6]
--operation mode is arithmetic

cnt_scan[6]_carry_eqn = A1L59;
cnt_scan[6]_lut_out = cnt_scan[6] $ (cnt_scan[6]_carry_eqn);
cnt_scan[6] = DFFEAS(cnt_scan[6]_lut_out, clk, rst, , , , , , );

--A1L79 is cnt_scan[6]~204
--operation mode is arithmetic

A1L79 = CARRY(!A1L59 # !cnt_scan[6]);


--cnt_scan[7] is cnt_scan[7]
--operation mode is arithmetic

cnt_scan[7]_carry_eqn = A1L79;
cnt_scan[7]_lut_out = cnt_scan[7] $ (!cnt_scan[7]_carry_eqn);
cnt_scan[7] = DFFEAS(cnt_scan[7]_lut_out, clk, rst, , , , , , );

--A1L99 is cnt_scan[7]~208
--operation mode is arithmetic

A1L99 = CARRY(cnt_scan[7] & (!A1L79));


--A1L642 is reduce_nor~198
--operation mode is normal

A1L642 = !cnt_scan[7] # !cnt_scan[6] # !cnt_scan[5] # !cnt_scan[4];


--cnt_scan[8] is cnt_scan[8]
--operation mode is arithmetic

cnt_scan[8]_carry_eqn = A1L99;
cnt_scan[8]_lut_out = cnt_scan[8] $ (cnt_scan[8]_carry_eqn);
cnt_scan[8] = DFFEAS(cnt_scan[8]_lut_out, clk, rst, , , , , , );

--A1L101 is cnt_scan[8]~212
--operation mode is arithmetic

A1L101 = CARRY(!A1L99 # !cnt_scan[8]);


--cnt_scan[9] is cnt_scan[9]
--operation mode is arithmetic

cnt_scan[9]_carry_eqn = A1L101;
cnt_scan[9]_lut_out = cnt_scan[9] $ (!cnt_scan[9]_carry_eqn);
cnt_scan[9] = DFFEAS(cnt_scan[9]_lut_out, clk, rst, , , , , , );

--A1L301 is cnt_scan[9]~216
--operation mode is arithmetic

A1L301 = CARRY(cnt_scan[9] & (!A1L101));


--cnt_scan[10] is cnt_scan[10]
--operation mode is arithmetic

cnt_scan[10]_carry_eqn = A1L301;
cnt_scan[10]_lut_out = cnt_scan[10] $ (cnt_scan[10]_carry_eqn);
cnt_scan[10] = DFFEAS(cnt_scan[10]_lut_out, clk, rst, , , , , , );

--A1L501 is cnt_scan[10]~220
--operation mode is arithmetic

A1L501 = CARRY(!A1L301 # !cnt_scan[10]);


--cnt_scan[11] is cnt_scan[11]
--operation mode is normal

cnt_scan[11]_carry_eqn = A1L501;
cnt_scan[11]_lut_out = cnt_scan[11] $ (!cnt_scan[11]_carry_eqn);
cnt_scan[11] = DFFEAS(cnt_scan[11]_lut_out, clk, rst, , , , , , );


--A1L742 is reduce_nor~199
--operation mode is normal

A1L742 = !cnt_scan[11] # !cnt_scan[10] # !cnt_scan[9] # !cnt_scan[8];


--A1L842 is reduce_nor~200
--operation mode is normal

A1L842 = !A1L542 & !A1L642 & !A1L742;


--phase1 is phase1
--operation mode is normal

phase1_lut_out = phase1 # !A1L242;
phase1 = DFFEAS(phase1_lut_out, clk, rst, , , , , phase1, );


--A1L441 is Mux~11426
--operation mode is normal

A1L441 = main_state[1] & (!main_state[0]);


--i2c_state[0] is i2c_state[0]
--operation mode is normal

i2c_state[0]_lut_out = A1L151 # A1L251 & (A1L441 # A1L741);
i2c_state[0] = DFFEAS(i2c_state[0]_lut_out, clk, rst, , , , , , );


--i2c_state[2] is i2c_state[2]
--operation mode is normal

i2c_state[2]_lut_out = i2c_state[2] & (!A1L251) # !i2c_state[2] & A1L351;
i2c_state[2] = DFFEAS(i2c_state[2]_lut_out, clk, rst, , !main_state[0], , , !main_state[1], );


--A1L372 is rtl~2793
--operation mode is normal

A1L372 = i2c_state[0] & (!i2c_state[2]);


--i2c_state[1] is i2c_state[1]
--operation mode is normal

i2c_state[1]_lut_out = A1L941 & (A1L451 # i2c_state[1] & !A1L541) # !A1L941 & (i2c_state[1] & !A1L541);
i2c_state[1] = DFFEAS(i2c_state[1]_lut_out, clk, rst, , , , , , );


--A1L232 is readData_reg[0]~213
--operation mode is normal

A1L232 = !i2c_state[1] # !A1L372 # !A1L441 # !phase1;


--inner_state[3] is inner_state[3]
--operation mode is normal

inner_state[3]_lut_out = i2c_state[2] & (A1L551) # !i2c_state[2] & A1L772;
inner_state[3] = DFFEAS(inner_state[3]_lut_out, clk, rst, , A1L082, A1L072, , , !main_state[1]);


--A1L621 is inner_state[2]~COMBOUT
--operation mode is normal

A1L621 = A1L182 & (A1L172) # !A1L182 & inner_state[2];

--inner_state[2] is inner_state[2]
--operation mode is normal

inner_state[2] = DFFEAS(A1L621, clk, rst, , A1L082, A1L272, , , !main_state[1]);


--inner_state[1] is inner_state[1]
--operation mode is normal

inner_state[1]_lut_out = i2c_state[2] & (A1L751) # !i2c_state[2] & A1L382;
inner_state[1] = DFFEAS(inner_state[1]_lut_out, clk, rst, , A1L082, A1L682, , , !main_state[1]);


--inner_state[0] is inner_state[0]
--operation mode is normal

inner_state[0]_lut_out = A1L661 # A1L761 # A1L741 & A1L171;
inner_state[0] = DFFEAS(inner_state[0]_lut_out, clk, rst, , , , , , );


--A1L332 is readData_reg[0]~214
--operation mode is normal

A1L332 = !inner_state[1] & !inner_state[0];


--A1L432 is readData_reg[0]~215
--operation mode is normal

A1L432 = !A1L232 & (inner_state[3] $ (inner_state[2] # !A1L332));


--A1L541 is Mux~11427
--operation mode is normal

A1L541 = !main_state[1] & !main_state[0];


--clk_div[3] is clk_div[3]
--operation mode is normal

clk_div[3]_lut_out = A1L3;
clk_div[3] = DFFEAS(clk_div[3]_lut_out, clk, rst, , , , , , );


--clk_div[5] is clk_div[5]
--operation mode is normal

clk_div[5]_lut_out = A1L5 & (clk_div[3] # !A1L152 # !A1L942);
clk_div[5] = DFFEAS(clk_div[5]_lut_out, clk, rst, , , , , , );


--clk_div[7] is clk_div[7]
--operation mode is normal

clk_div[7]_lut_out = A1L7;
clk_div[7] = DFFEAS(clk_div[7]_lut_out, clk, rst, , , , , , );


--clk_div[2] is clk_div[2]
--operation mode is normal

clk_div[2]_lut_out = A1L8 & (clk_div[3] # !A1L152 # !A1L942);
clk_div[2] = DFFEAS(clk_div[2]_lut_out, clk, rst, , , , , , );


--A1L942 is reduce_nor~201
--operation mode is normal

A1L942 = clk_div[0] & clk_div[5] & !clk_div[7] & !clk_div[2];


--clk_div[4] is clk_div[4]
--operation mode is normal

clk_div[4]_lut_out = A1L01;
clk_div[4] = DFFEAS(clk_div[4]_lut_out, clk, rst, , , , , , );


--clk_div[6] is clk_div[6]
--operation mode is normal

clk_div[6]_lut_out = A1L21 & (clk_div[3] # !A1L152 # !A1L942);
clk_div[6] = DFFEAS(clk_div[6]_lut_out, clk, rst, , , , , , );


--A1L022 is phase2~36
--operation mode is normal

A1L022 = clk_div[4] & (!cnt_scan[1] & !clk_div[6]);


--phase3 is phase3
--operation mode is normal

phase3_lut_out = phase3 # !A1L342;
phase3 = DFFEAS(phase3_lut_out, clk, rst, , , , , phase3, );


--A1L231 is main_state[0]~1739
--operation mode is normal

A1L231 = inner_state[2] & inner_state[0] # !inner_state[2] & inner_state[1] & (inner_state[0] # phase3);


--sda_buf is sda_buf
--operation mode is normal

sda_buf_lut_out = !A1L891 & (!A1L802 & !A1L012 # !A1L741);
sda_buf = DFFEAS(sda_buf_lut_out, clk, rst, , , , , , );


--A1L641 is Mux~11428
--operation mode is normal

A1L641 = inner_state[0] & (!inner_state[1] & !inner_state[2]);


--A1L331 is main_state[0]~1740
--operation mode is normal

A1L331 = !sda_buf & phase1 & (i2c_state[1] # A1L641);


--A1L431 is main_state[0]~1741
--operation mode is normal

A1L431 = i2c_state[1] & (inner_state[0] & !A1L231 & A1L331 # !inner_state[0] & A1L231) # !i2c_state[1] & (A1L331);


--A1L531 is main_state[0]~1742
--operation mode is normal

A1L531 = inner_state[3] & !A1L431 & (!i2c_state[1] # !i2c_state[0]) # !inner_state[3] & (!i2c_state[1] # !i2c_state[0]);


--A1L741 is Mux~11429
--operation mode is normal

A1L741 = main_state[0] & (!i2c_state[2] & !main_state[1]);


--A1L841 is Mux~11430
--operation mode is normal

A1L841 = i2c_state[2] & i2c_state[0];