i2c.map.rpt

FPGA使用I2C总线

;     -- 4 input functions                    ; 116   ;
;     -- 3 input functions                    ; 40    ;
;     -- 2 input functions                    ; 66    ;
;     -- 1 input functions                    ; 6     ;
;     -- 0 input functions                    ; 0     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 219   ;
;     -- arithmetic mode                      ; 35    ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 7     ;
;     -- asynchronous clear/load mode         ; 69    ;
;                                             ;       ;
; Total registers                             ; 69    ;
; Total logic cells in carry chains           ; 38    ;
; I/O pins                                    ; 21    ;
; Maximum fan-out node                        ; clk   ;
; Maximum fan-out                             ; 69    ;
; Total fan-out                               ; 947   ;
; Average fan-out                             ; 3.44  ;
+---------------------------------------------+-------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                  ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; |i2c                       ; 254 (254)   ; 69           ; 0          ; 21   ; 0            ; 185 (185)    ; 26 (26)           ; 43 (43)          ; 38 (38)         ; 0 (0)      ; |i2c                ; work         ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+--------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                             ;
+---------------------------------------+----------------------------------------+
; Register name                         ; Reason for Removal                     ;
+---------------------------------------+----------------------------------------+
; writeData_reg[4..6]                   ; Merged with writeData_reg[7]           ;
; writeData_reg[7]                      ; Stuck at GND due to stuck port data_in ;
; clk_div[0]                            ; Merged with cnt_scan[0]                ;
; clk_div[1]                            ; Merged with cnt_scan[1]                ;
; Total Number of Removed Registers = 6 ;                                        ;
+---------------------------------------+----------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 69    ;
; Number of registers using Synchronous Clear  ; 3     ;
; Number of registers using Synchronous Load   ; 4     ;
; Number of registers using Asynchronous Clear ; 69    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 40    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; scl_xhdl1                              ; 2       ;
; en_xhdl3[1]                            ; 8       ;
; writeData_reg[0]                       ; 2       ;
; writeData_reg[2]                       ; 2       ;
; sda_buf                                ; 21      ;
; Total number of inverted registers = 5 ;         ;
+----------------------------------------+---------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 12:1               ; 8 bits    ; 64 LEs        ; 0 LEs                ; 64 LEs                 ; Yes        ; |i2c|readData_reg[5]       ;
; 33:1               ; 2 bits    ; 44 LEs        ; 6 LEs                ; 38 LEs                 ; Yes        ; |i2c|main_state[0]         ;
; 4:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; No         ; |i2c|Mux111                ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.1 Build 178 06/25/2007 Service Pack 1 SJ Full Version
    Info: Processing started: Wed Oct 10 16:40:08 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off i2c -c i2c
Info: Found 2 design units, including 1 entities, in source file i2c.vhd
    Info: Found design unit 1: i2c-translated
    Info: Found entity 1: i2c
Info: Elaborating entity "i2c" for the top level hierarchy
Warning (10631): VHDL Process Statement warning at i2c.vhd(145): inferring latch(es) for signal or variable "addr", which holds its previous value in one or more paths through the process
Info (10041): Inferred latch for "addr[0]" at i2c.vhd(145)
Info (10041): Inferred latch for "addr[1]" at i2c.vhd(145)
Info (10041): Inferred latch for "addr[2]" at i2c.vhd(145)
Info (10041): Inferred latch for "addr[3]" at i2c.vhd(145)
Info (10041): Inferred latch for "addr[4]" at i2c.vhd(145)
Info (10041): Inferred latch for "addr[5]" at i2c.vhd(145)
Info (10041): Inferred latch for "addr[6]" at i2c.vhd(145)
Info (10041): Inferred latch for "addr[7]" at i2c.vhd(145)
Info: Duplicate registers merged to single register
    Info: Duplicate register "writeData_reg[4]" merged to single register "writeData_reg[7]"
    Info: Duplicate register "writeData_reg[5]" merged to single register "writeData_reg[7]"
    Info: Duplicate register "writeData_reg[6]" merged to single register "writeData_reg[7]"
Warning: Reduced register "writeData_reg[7]" with stuck data_in port to stuck value GND
Info: Duplicate registers merged to single register
    Info: Duplicate register "clk_div[0]" merged to single register "cnt_scan[0]"
    Info: Duplicate register "clk_div[1]" merged to single register "cnt_scan[1]"
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "lowbit" stuck at GND
    Warning: Pin "seg_data[0]" stuck at VCC
Info: Registers with preset signals will power-up high
Info: Implemented 275 device resources after synthesis - the final resource count might be different
    Info: Implemented 8 input pins
    Info: Implemented 12 output pins
    Info: Implemented 1 bidirectional pins
    Info: Implemented 254 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings
    Info: Allocated 153 megabytes of memory during processing
    Info: Processing ended: Wed Oct 10 16:40:30 2007
    Info: Elapsed time: 00:00:22