i2c.fit.eqn

FPGA使用I2C总线

--operation mode is normal

inner_state[2] = DFFEAS(A1L851, GLOBAL(clk), GLOBAL(rst), , A1L213, A1L403, , , !main_state[1]);


--inner_state[1] is inner_state[1] at LC_X15_Y5_N7
--operation mode is normal

inner_state[1]_lut_out = i2c_state[2] & A1L981 # !i2c_state[2] & (A1L513);
inner_state[1] = DFFEAS(inner_state[1]_lut_out, GLOBAL(clk), GLOBAL(rst), , A1L213, A1L813, , , !main_state[1]);


--inner_state[0] is inner_state[0] at LC_X13_Y5_N0
--operation mode is normal

inner_state[0]_lut_out = A1L891 # A1L991 # A1L971 & A1L302;
inner_state[0] = DFFEAS(inner_state[0]_lut_out, GLOBAL(clk), GLOBAL(rst), , , , , , );


--A1L562 is readData_reg[0]~214 at LC_X15_Y6_N4
--operation mode is normal

A1L562 = !inner_state[1] & !inner_state[0];


--A1L662 is readData_reg[0]~215 at LC_X16_Y6_N2
--operation mode is normal

A1L662 = !A1L462 & (inner_state[3] $ (inner_state[2] # !A1L562));


--A1L771 is Mux~11427 at LC_X15_Y7_N5
--operation mode is normal

A1L771 = !main_state[1] & !main_state[0];


--clk_div[5] is clk_div[5] at LC_X14_Y8_N6
--operation mode is normal

clk_div[5]_lut_out = A1L7 & (clk_div[3] # !A1L382 # !A1L182);
clk_div[5] = DFFEAS(clk_div[5]_lut_out, GLOBAL(clk), GLOBAL(rst), , , , , , );


--clk_div[2] is clk_div[2] at LC_X14_Y8_N8
--operation mode is normal

clk_div[2]_lut_out = A1L11 & (clk_div[3] # !A1L182 # !A1L382);
clk_div[2] = DFFEAS(clk_div[2]_lut_out, GLOBAL(clk), GLOBAL(rst), , , , , , );


--A1L182 is reduce_nor~201 at LC_X14_Y8_N9
--operation mode is normal

A1L182 = clk_div[5] & clk_div[0] & !clk_div[7] & !clk_div[2];


--clk_div[6] is clk_div[6] at LC_X14_Y8_N4
--operation mode is normal

clk_div[6]_lut_out = A1L81 & (clk_div[3] # !A1L182 # !A1L382);
clk_div[6] = DFFEAS(clk_div[6]_lut_out, GLOBAL(clk), GLOBAL(rst), , , , , , );


--A1L252 is phase2~36 at LC_X13_Y8_N9
--operation mode is normal

clk_div[4]_qfbk = clk_div[4];
A1L252 = !clk_div[6] & clk_div[4]_qfbk & !cnt_scan[1];

--clk_div[4] is clk_div[4] at LC_X13_Y8_N9
--operation mode is normal

clk_div[4] = DFFEAS(A1L252, GLOBAL(clk), GLOBAL(rst), , , A1L41, , , VCC);


--phase3 is phase3 at LC_X14_Y5_N1
--operation mode is normal

phase3_lut_out = phase3 # !A1L572;
phase3 = DFFEAS(phase3_lut_out, GLOBAL(clk), GLOBAL(rst), , , , , phase3, );


--A1L461 is main_state[0]~1739 at LC_X13_Y4_N0
--operation mode is normal

A1L461 = inner_state[2] & inner_state[0] # !inner_state[2] & inner_state[1] & (inner_state[0] # phase3);


--sda_buf is sda_buf at LC_X14_Y5_N9
--operation mode is normal

sda_buf_lut_out = !A1L032 & (!A1L042 & !A1L242 # !A1L971);
sda_buf = DFFEAS(sda_buf_lut_out, GLOBAL(clk), GLOBAL(rst), , , , , , );


--A1L871 is Mux~11428 at LC_X15_Y5_N8
--operation mode is normal

A1L871 = !inner_state[1] & !inner_state[2] & inner_state[0];


--A1L561 is main_state[0]~1740 at LC_X13_Y4_N5
--operation mode is normal

A1L561 = phase1 & !sda_buf & (i2c_state[1] # A1L871);


--A1L661 is main_state[0]~1741 at LC_X13_Y4_N6
--operation mode is normal

A1L661 = i2c_state[1] & (inner_state[0] & !A1L461 & A1L561 # !inner_state[0] & A1L461) # !i2c_state[1] & (A1L561);


--A1L761 is main_state[0]~1742 at LC_X13_Y4_N7
--operation mode is normal

A1L761 = i2c_state[0] & !i2c_state[1] & (!A1L661 # !inner_state[3]) # !i2c_state[0] & (!A1L661 # !inner_state[3]);


--A1L971 is Mux~11429 at LC_X14_Y6_N0
--operation mode is normal

A1L971 = !i2c_state[2] & (!main_state[1] & main_state[0]);


--A1L081 is Mux~11430 at LC_X14_Y6_N7
--operation mode is normal

A1L081 = i2c_state[2] & i2c_state[0];


--A1L603 is rtl~2794 at LC_X12_Y6_N0
--operation mode is normal

A1L603 = inner_state[3] & (!inner_state[0] & phase3);


--A1L861 is main_state[0]~1743 at LC_X13_Y7_N4
--operation mode is normal

A1L861 = inner_state[2] # !A1L603 # !i2c_state[0] # !inner_state[1];


--A1L961 is main_state[0]~1744 at LC_X13_Y7_N7
--operation mode is normal

A1L961 = sda_buf # !A1L871 # !inner_state[3] # !phase1;


--A1L071 is main_state[0]~1745 at LC_X13_Y7_N5
--operation mode is normal

A1L071 = A1L081 # i2c_state[1] & (A1L861) # !i2c_state[1] & A1L961;


--cnt_delay[18] is cnt_delay[18] at LC_X11_Y6_N3
--operation mode is normal

cnt_delay[18]_lut_out = A1L672 & A1L12;
cnt_delay[18] = DFFEAS(cnt_delay[18]_lut_out, GLOBAL(clk), GLOBAL(rst), , start_delaycnt, , , , );


--cnt_delay[13] is cnt_delay[13] at LC_X11_Y6_N2
--operation mode is normal

cnt_delay[13]_lut_out = A1L672 & A1L42;
cnt_delay[13] = DFFEAS(cnt_delay[13]_lut_out, GLOBAL(clk), GLOBAL(rst), , start_delaycnt, , , , );


--cnt_delay[12] is cnt_delay[12] at LC_X10_Y6_N7
--operation mode is normal

cnt_delay[12]_lut_out = A1L672 & (A1L72);
cnt_delay[12] = DFFEAS(cnt_delay[12]_lut_out, GLOBAL(clk), GLOBAL(rst), , start_delaycnt, , , , );


--cnt_delay[10] is cnt_delay[10] at LC_X10_Y6_N5
--operation mode is normal

cnt_delay[10]_lut_out = A1L672 & (A1L03);
cnt_delay[10] = DFFEAS(cnt_delay[10]_lut_out, GLOBAL(clk), GLOBAL(rst), , start_delaycnt, , , , );


--A1L282 is reduce_nor~202 at LC_X11_Y6_N9
--operation mode is normal

A1L282 = !cnt_delay[12] # !cnt_delay[18] # !cnt_delay[13] # !cnt_delay[10];


--cnt_delay[16] is cnt_delay[16] at LC_X11_Y6_N4
--operation mode is normal

cnt_delay[16]_lut_out = GND;
cnt_delay[16] = DFFEAS(cnt_delay[16]_lut_out, GLOBAL(clk), GLOBAL(rst), , start_delaycnt, A1L63, , , VCC);


--cnt_delay[15] is cnt_delay[15] at LC_X11_Y6_N0
--operation mode is normal

cnt_delay[15]_lut_out = GND;
cnt_delay[15] = DFFEAS(cnt_delay[15]_lut_out, GLOBAL(clk), GLOBAL(rst), , start_delaycnt, A1L93, , , VCC);


--cnt_delay[14] is cnt_delay[14] at LC_X11_Y6_N1
--operation mode is normal

cnt_delay[14]_lut_out = GND;
cnt_delay[14] = DFFEAS(cnt_delay[14]_lut_out, GLOBAL(clk), GLOBAL(rst), , start_delaycnt, A1L24, , , VCC);


--A1L452 is process2~149 at LC_X11_Y6_N5
--operation mode is normal

cnt_delay[17]_qfbk = cnt_delay[17];
A1L452 = !cnt_delay[16] & !cnt_delay[15] & !cnt_delay[17]_qfbk & !cnt_delay[14];

--cnt_delay[17] is cnt_delay[17] at LC_X11_Y6_N5
--operation mode is normal

cnt_delay[17] = DFFEAS(A1L452, GLOBAL(clk), GLOBAL(rst), , start_delaycnt, A1L33, , , VCC);


--cnt_delay[9] is cnt_delay[9] at LC_X10_Y6_N2
--operation mode is normal

cnt_delay[9]_lut_out = GND;
cnt_delay[9] = DFFEAS(cnt_delay[9]_lut_out, GLOBAL(clk), GLOBAL(rst), , start_delaycnt, A1L74, , , VCC);


--cnt_delay[7] is cnt_delay[7] at LC_X9_Y5_N5
--operation mode is normal

cnt_delay[7]_lut_out = A1L94;
cnt_delay[7] = DFFEAS(cnt_delay[7]_lut_out, GLOBAL(clk), GLOBAL(rst), , start_delaycnt, , , , );


--cnt_delay[6] is cnt_delay[6] at LC_X10_Y6_N3
--operation mode is normal

cnt_delay[6]_lut_out = GND;
cnt_delay[6] = DFFEAS(cnt_delay[6]_lut_out, GLOBAL(clk), GLOBAL(rst), , start_delaycnt, A1L25, , , VCC);


--A1L552 is process2~150 at LC_X10_Y6_N6
--operation mode is normal

cnt_delay[11]_qfbk = cnt_delay[11];
A1L552 = !cnt_delay[6] & !cnt_delay[9] & !cnt_delay[11]_qfbk & !cnt_delay[7];

--cnt_delay[11] is cnt_delay[11] at LC_X10_Y6_N6
--operation mode is normal

cnt_delay[11] = DFFEAS(A1L552, GLOBAL(clk), GLOBAL(rst), , start_delaycnt, A1L44, , , VCC);


--cnt_delay[4] is cnt_delay[4] at LC_X9_Y5_N4
--operation mode is normal

cnt_delay[4]_lut_out = A1L85;
cnt_delay[4] = DFFEAS(cnt_delay[4]_lut_out, GLOBAL(clk), GLOBAL(rst), , start_delaycnt, , , , );


--cnt_delay[3] is cnt_delay[3] at LC_X9_Y5_N2
--operation mode is normal

cnt_delay[3]_lut_out = GND;
cnt_delay[3] = DFFEAS(cnt_delay[3]_lut_out, GLOBAL(clk), GLOBAL(rst), , start_delaycnt, A1L06, , , VCC);


--cnt_delay[2] is cnt_delay[2] at LC_X9_Y5_N9
--operation mode is normal

cnt_delay[2]_lut_out = GND;
cnt_delay[2] = DFFEAS(cnt_delay[2]_lut_out, GLOBAL(clk), GLOBAL(rst), , start_delaycnt, A1L36, , , VCC);


--A1L652 is process2~151 at LC_X9_Y5_N6
--operation mode is normal

cnt_delay[5]_qfbk = cnt_delay[5];
A1L652 = !cnt_delay[4] & !cnt_delay[3] & !cnt_delay[5]_qfbk & !cnt_delay[2];

--cnt_delay[5] is cnt_delay[5] at LC_X9_Y5_N6
--operation mode is normal

cnt_delay[5] = DFFEAS(A1L652, GLOBAL(clk), GLOBAL(rst), , start_delaycnt, A1L55, , , VCC);


--cnt_delay[0] is cnt_delay[0] at LC_X10_Y6_N0
--operation mode is normal

cnt_delay[0]_lut_out = A1L672 & (A1L96);
cnt_delay[0] = DFFEAS(cnt_delay[0]_lut_out, GLOBAL(clk), GLOBAL(rst), , start_delaycnt, , , , );


--A1L752 is process2~152 at LC_X10_Y6_N8
--operation mode is normal

cnt_delay[1]_qfbk = cnt_delay[1];
A1L752 = !cnt_delay[0] & !cnt_delay[1]_qfbk;

--cnt_delay[1] is cnt_delay[1] at LC_X10_Y6_N8
--operation mode is normal

cnt_delay[1] = DFFEAS(A1L752, GLOBAL(clk), GLOBAL(rst), , start_delaycnt, A1L66, , , VCC);


--A1L852 is process2~153 at LC_X10_Y6_N4
--operation mode is normal

A1L852 = A1L752 & A1L452 & A1L552 & A1L652;


--cnt_delay[8] is cnt_delay[8] at LC_X9_Y5_N0
--operation mode is normal

cnt_delay[8]_lut_out = A1L672 & A1L27;
cnt_delay[8] = DFFEAS(cnt_delay[8]_lut_out, GLOBAL(clk), GLOBAL(rst), , start_delaycnt, , , , );


--cnt_delay[19] is cnt_delay[19] at LC_X11_Y6_N8
--operation mode is normal

cnt_delay[19]_lut_out = A1L672 & A1L57;
cnt_delay[19] = DFFEAS(cnt_delay[19]_lut_out, GLOBAL(clk), GLOBAL(rst), , start_delaycnt, , , , );


--A1L672 is reduce_nor~5 at LC_X10_Y6_N9
--operation mode is normal

A1L672 = A1L282 # !cnt_delay[8] # !A1L852 # !cnt_delay[19];


--A1L171 is main_state[0]~1746 at LC_X14_Y6_N8
--operation mode is normal

A1L171 = wr_input & rd_input;


--A1L271 is main_state[0]~1747 at LC_X14_Y6_N1
--operation mode is normal

A1L271 = main_state[1] & (A1L071) # !main_state[1] & (A1L171 # A1L672);


--A1L371 is main_state[0]~1748 at LC_X14_Y6_N2
--operation mode is normal

A1L371 = main_state[0] & A1L971 & A1L761 # !main_state[0] & (A1L271 # A1L971 & A1L761);


--A1L382 is reduce_nor~203 at LC_X13_Y8_N8
--operation mode is normal

A1L382 = !clk_div[4] & cnt_scan[1] & clk_div[6];


--A1L1 is add~549 at LC_X13_Y8_N0
--operation mode is arithmetic

A1L1 = !clk_div[0];

--A1L2 is add~551 at LC_X13_Y8_N0
--operation mode is arithmetic

A1L2_cout_0 = clk_div[0];
A1L2 = CARRY(A1L2_cout_0);

--A1L3 is add~551COUT1_712 at LC_X13_Y8_N0
--operation mode is arithmetic

A1L3_cout_1 = clk_div[0];
A1L3 = CARRY(A1L3_cout_1);


--A1L482 is reduce_nor~204 at LC_X14_Y8_N1
--operation mode is normal

clk_div[7]_qfbk = clk_div[7];
A1L482 = !clk_div[5] & !clk_div[0] & !clk_div[7]_qfbk & !clk_div[2];

--clk_div[7] is clk_div[7] at LC_X14_Y8_N1
--operation mode is normal

clk_div[7] = DFFEAS(A1L482, GLOBAL(clk), GLOBAL(rst), , , A1L01, , , VCC);


--A1L472 is reduce_nor~1 at LC_X14_Y8_N5
--operation mode is normal

clk_div[3]_qfbk = clk_div[3];
A1L472 = !A1L482 # !clk_div[3]_qfbk # !A1L252;

--clk_div[3] is clk_div[3] at LC_X14_Y8_N5
--operation mode is normal

clk_div[3] = DFFEAS(A1L472, GLOBAL(clk), GLOBAL(rst), , , A1L4, , , VCC);


--A1L181 is Mux~11431 at LC_X12_Y7_N2
--operation mode is normal

A1L181 = inner_state[3] & A1L871 & phase3;


--A1L281 is Mux~11432 at LC_X14_Y7_N5
--operation mode is normal

A1L281 = i2c_state[2] # i2c_state[1] # !A1L181;


--A1L381 is Mux~11433 at LC_X14_Y7_N6
--operation mode is normal

A1L381 = i2c_state[0] & (main_state[1] & (main_state[0] # A1L281) # !main_state[1] & main_state[0] & A1L281);


--A1L481 is Mux~11434 at LC_X14_Y7_N4
--operation mode is normal

A1L481 = !i2c_state[1] & !i2c_state[0] & A1L181;


--A1L581 is Mux~11436 at LC_X14_Y7_N3
--operation mode is normal

A1L581 = !i2c_state[1] & i2c_state[0] & A1L181;


--A1L681 is Mux~11437 at LC_X14_Y7_N9
--operation mode is normal

A1L681 = i2c_state[2] & !main_state[0] & main_state[1] & !i2c_state[0] # !i2c_state[2] & main_state[0] & !main_state[1] & i2c_state[0];


--A1L703 is rtl~2795 at LC_X13_Y4_N8
--operation mode is normal

A1L703 = inner_state[0] & inner_state[2] & inner_state[1] & phase3;


--A1L803 is rtl~2796 at LC_X13_Y4_N3
--operation mode is normal

A1L803 = inner_state[0] & !inner_state[2] & !inner_state[1] & phase3;


--A1L903 is rtl~2797 at LC_X13_Y4_N9
--operation mode is normal

A1L903 = A1L703 # inner_state[3] & (i2c_state[1] # !A1L803);


--A1L781 is Mux~11439 at LC_X13_Y4_N2
--operation mode is normal

A1L781 = A1L703 # !A1L803 & inner_state[3];


--A1L203 is rtl~1 at LC_X13_Y4_N4
--operation mode is normal

A1L203 = main_state[0] & A1L903;


--A1L013 is rtl~2798 at LC_X14_Y4_N6
--operation mode is normal

A1L013 = !i2c_state[2] & !main_state[1] & (!i2c_state[1] # !i2c_state[0]);


--A1L113 is rtl~2799 at LC_X14_Y4_N7
--operation mode is normal

A1L113 = !i2c_state[0] & !i2c_state[1] # !main_state[1];


--A1L213 is rtl~2800 at LC_X14_Y4_N4
--operation mode is normal

A1L213 = A1L013 # !main_state[0] & (A1L113 # A1L503);


--A1L303 is rtl~10 at LC_X15_Y4_N7
--operation mode is normal

A1L303 = phase3 $ inner_state[2];


--A1L403 is rtl~13 at LC_X15_Y4_N2
--operation mode is normal

A1L403 = main_state[0] & A1L851;


--A1L313 is rtl~2801 at LC_X14_Y4_N0
--operation mode is normal

A1L313 = !inner_state[3] & inner_state[0] & inner_state[1];


--A1L413 is rtl~2802 at LC_X15_Y4_N4
--operation mode is normal

A1L413 = i2c_state[1] & !inner_state[2];


--A1L881 is Mux~11440 at LC_X13_Y5_N3
--operation mode is normal

A1L881 = inner_state[0] & (phase3);


--A1L513 is rtl~2803 at LC_X15_Y4_N0
--operation mode is normal

A1L513 = inner_state[1] & (inner_state[3] # !A1L881) # !inner_state[1] & A1L881 & (A1L413 # !inner_state[3]);


--A1L981 is Mux~11441 at LC_X16_Y5_N7
--operation mode is normal

A1L981 = inner_state[1] $ (phase3 & !inner_state[3] & inner_state[0]);


--A1L613 is rtl~2804 at LC_X15_Y7_N0
--operation mode is normal

A1L613 = !inner_state[2] & (!phase1 & i2c_state[1]);