multi_fre.vhd

multifrequency program

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-- Company: 
-- Engineer:
--
-- Create Date:    11:03:41 10/18/07
-- Design Name:    
-- Module Name:    multi_fre - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity multi_fre is
  port(clk,en:in std_logic;
          clk1,clk3:out std_logic);
end multi_fre;

architecture Behavioral of multi_fre is

begin
     process(clk,en)
        variable count:integer range 0 to 4 :=0;
     begin
          if en='0' then
               NUll;
          elsif (rising_edge(clk)) then
                 count:=count+1;
               if count=4 then
                    clk1<='1';
						  count:=0;
               else
                     clk1<='0';
               end if;
               if (count=1 or count=3or count=5 ) then
                              clk3<='1';
               else
                            clk3<='0';
               end if;
           end if;
       end process;

end Behavioral;