multi_fre_timesim.vhd

采样时钟程序:在波特率为9600的采样时钟程序-multifrequency program. The baud rate for the 9600 multifrequency program

--------------------------------------------------------------------------------
-- Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor: Xilinx
-- \   \   \/     Version: H.38
--  \   \         Application: netgen
--  /   /         Filename: multi_fre_timesim.vhd
-- /___/   /\     Timestamp: Thu Oct 18 11:18:46 2007
-- \   \  /  \ 
--  \___\/\___\
--             
-- Command: -intstyle ise -s 4 -pcf multi_fre.pcf -rpw 100 -tpw 0 -ar Structure -xon true -w -ofmt vhdl -sim multi_fre.ncd multi_fre_timesim.vhd 
-- Device: 3s1000ft256-4 (PRODUCTION 1.35 2005-01-22)
-- Design Name: multi_fre
--             
-- Purpose:    
--     This VHDL netlist is a verification model and uses simulation 
--     primitives which may not represent the true implementation of the 
--     device, however the netlist is functionally correct and should not 
--     be modified. This file cannot be synthesized and should only be used 
--     with supported simulation tools.
--             
-- Reference:  
--     Development System Reference Guide, Chapter 23
--     Synthesis and Verification Design Guide, Chapter 6
--             
--------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity multi_fre is
  port (
    clk : in STD_LOGIC := 'X'; 
    en : in STD_LOGIC := 'X'; 
    clk1 : out STD_LOGIC; 
    clk3 : out STD_LOGIC 
  );
end multi_fre;

architecture Structure of multi_fre is
  signal en_IBUF : STD_LOGIC; 
  signal clk_BUFGP_IBUFG : STD_LOGIC; 
  signal clk_BUFGP : STD_LOGIC; 
  signal count_0_Q : STD_LOGIC; 
  signal GLOBAL_LOGIC1 : STD_LOGIC; 
  signal count_1_Q : STD_LOGIC; 
  signal GSR : STD_LOGIC; 
  signal GTS : STD_LOGIC; 
  signal en_INBUF : STD_LOGIC; 
  signal clk_INBUF : STD_LOGIC; 
  signal clk1_ENABLE : STD_LOGIC; 
  signal clk1_O : STD_LOGIC; 
  signal clk3_ENABLE : STD_LOGIC; 
  signal clk3_O : STD_LOGIC; 
  signal clk_BUFGP_BUFG_S_INVNOT : STD_LOGIC; 
  signal count_0_DXMUX : STD_LOGIC; 
  signal Q_n00061_O : STD_LOGIC; 
  signal count_0_DYMUX : STD_LOGIC; 
  signal Q_n0000_1_1_O : STD_LOGIC; 
  signal count_0_CLKINV : STD_LOGIC; 
  signal count_0_CEINV : STD_LOGIC; 
  signal clk1_OUTPUT_OFF_O1INV : STD_LOGIC; 
  signal clk1_OUTPUT_OFF_OCEINV : STD_LOGIC; 
  signal clk1_OBUF : STD_LOGIC; 
  signal clk1_OUTPUT_OTCLK1INV : STD_LOGIC; 
  signal clk1_OUTPUT_OFF_OFF1_RST : STD_LOGIC; 
  signal count_0_FFY_RST : STD_LOGIC; 
  signal count_0_FFX_RST : STD_LOGIC; 
  signal GND : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
begin
  en_IBUF_0 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => en,
      O => en_INBUF
    );
  en_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => en_INBUF,
      O => en_IBUF
    );
  clk_BUFGP_IBUFG_1 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => clk,
      O => clk_INBUF
    );
  clk_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => clk_INBUF,
      O => clk_BUFGP_IBUFG
    );
  clk1_OBUF_2 : X_TRI_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => clk1_O,
      CTL => clk1_ENABLE,
      O => clk1
    );
  clk1_ENABLEINV : X_INV_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GTS,
      O => clk1_ENABLE
    );
  clk3_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => clk3_O,
      CTL => clk3_ENABLE,
      O => clk3
    );
  clk3_ENABLEINV : X_INV_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GTS,
      O => clk3_ENABLE
    );
  clk_BUFGP_BUFG : X_BUFGMUX
    port map (
      I0 => clk_BUFGP_IBUFG,
      I1 => GND,
      S => clk_BUFGP_BUFG_S_INVNOT,
      O => clk_BUFGP,
      GSR => GSR
    );
  clk_BUFGP_BUFG_SINV : X_INV_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GLOBAL_LOGIC1,
      O => clk_BUFGP_BUFG_S_INVNOT
    );
  count_0_DXMUX_3 : X_INV_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => count_0_Q,
      O => count_0_DXMUX
    );
  count_0_DYMUX_4 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Q_n0000_1_1_O,
      O => count_0_DYMUX
    );
  count_0_CLKINV_5 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => clk_BUFGP,
      O => count_0_CLKINV
    );
  count_0_CEINV_6 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => en_IBUF,
      O => count_0_CEINV
    );
  Q_n0000_1_1 : X_LUT4
    generic map(
      INIT => X"33CC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => count_0_Q,
      ADR2 => VCC,
      ADR3 => count_1_Q,
      O => Q_n0000_1_1_O
    );
  clk1_OUTPUT_OFF_O1INV_7 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Q_n00061_O,
      O => clk1_OUTPUT_OFF_O1INV
    );
  clk1_OUTPUT_OFF_OCEINV_8 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => en_IBUF,
      O => clk1_OUTPUT_OFF_OCEINV
    );
  clk1_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => clk1_OBUF,
      O => clk1_O
    );
  clk1_OUTPUT_OTCLK1INV_9 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => clk_BUFGP,
      O => clk1_OUTPUT_OTCLK1INV
    );
  clk1_10 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => clk1_OUTPUT_OFF_O1INV,
      CE => clk1_OUTPUT_OFF_OCEINV,
      CLK => clk1_OUTPUT_OTCLK1INV,
      SET => GND,
      RST => clk1_OUTPUT_OFF_OFF1_RST,
      O => clk1_OBUF
    );
  clk1_OUTPUT_OFF_OFF1_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GSR,
      O => clk1_OUTPUT_OFF_OFF1_RST
    );
  count_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => count_0_DYMUX,
      CE => count_0_CEINV,
      CLK => count_0_CLKINV,
      SET => GND,
      RST => count_0_FFY_RST,
      O => count_1_Q
    );
  count_0_FFY_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GSR,
      O => count_0_FFY_RST
    );
  Q_n00061 : X_LUT4
    generic map(
      INIT => X"CC00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => count_0_Q,
      ADR2 => VCC,
      ADR3 => count_1_Q,
      O => Q_n00061_O
    );
  count_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => count_0_DXMUX,
      CE => count_0_CEINV,
      CLK => count_0_CLKINV,
      SET => GND,
      RST => count_0_FFX_RST,
      O => count_0_Q
    );
  count_0_FFX_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GSR,
      O => count_0_FFX_RST
    );
  GLOBAL_LOGIC1_VCC : X_ONE
    port map (
      O => GLOBAL_LOGIC1
    );
  clk3_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => count_0_Q,
      O => clk3_O
    );
  NlwBlock_multi_fre_GND : X_ZERO
    port map (
      O => GND
    );
  NlwBlock_multi_fre_VCC : X_ONE
    port map (
      O => VCC
    );
  NlwBlockROC : X_ROC
    generic map (ROC_WIDTH => 100 ns)
    port map (O => GSR);
  NlwBlockTOC : X_TOC
    port map (O => GTS);

end Structure;