unary_op.log.txt

来自「將Verilog設計轉成VHDL設計的程式」· 文本 代码 · 共 68 行

function verilog_unary_and(val: Bit_Vector)
	return bit is
	variable result: bit ;
	begin
		result:=val(0);
		for i in 1 to (val'length-1) loop
				result := result and val(i);
			end loop;
		return result;
	end verilog_unary_and;	
 
function verilog_unary_nand(val: Bit_Vector)
	return bit is
	variable result: bit ;
	begin
		result:=val(0);
		for i in 1 to (val'length-1) loop
				result := result nand val(i);
			end loop;
		return result;
	end verilog_unary_nand;	
		
function verilog_unary_or(val: Bit_Vector)
	return bit is
	variable result: bit ;
	begin
		result:=val(0);
		for i in 1 to (val'length-1) loop
				result := result or val(i);
			end loop;
		return result;
	end verilog_unary_or;	

function verilog_unary_nor(val: Bit_Vector)
	return bit is
	variable result: bit ;
	begin
		result:=val(0);
		for i in 1 to (val'length-1) loop
				result := result nor val(i);
			end loop;
		return result;
	end verilog_unary_nor;

function verilog_unary_xor(val: Bit_Vector)
	return bit is
	variable result: bit ;
	begin
		result:=val(0);
		for i in 1 to (val'length-1) loop
				result := result xor val(i);
			end loop;
		return result;
	end verilog_unary_xor;

function verilog_unary_nxor(val: Bit_Vector)
	return bit is
	variable result: bit ;
	begin
		result:=val(0);
		for i in 1 to (val'length-1) loop
				result :=not (result xor val(i));
			end loop;
		return result;
	end verilog_unary_nxor;