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📄 verilog-y

📁 將Verilog設計轉成VHDL設計的程式
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%{#include <stdio.h>#include <string.h>#include <stdlib.h>#include <unistd.h>#include "../classes/List.h"#include "../classes/Util.h"#include "../classes/IODecl.h"#include "../classes/Module.h"#include "../classes/BitVec.h"extern int yylex();extern int yylineno;extern int yyparse();void yyerror(const char*);char* beginproc();void endproc();extern FILE* yyin;FILE *debug;FILE *output;FILE *input;FILE *fp;Tab *t;extern FILE *output;extern FILE *debug;void *buggy;short 	shift_l = 0,	shift_r = 0,	unary_or = 0,	unary_and = 0,	unary_nor = 0,	unary_nand = 0,	unary_xor = 0,	unary_nxor = 0;%}%union {	int		number;	double		real;	char*		char_ptr;	ListP 		list;	IODeclP		io_decl;	MItemP		m_item;	ModuleP		module;	PDeclP		p_decl;	PBDeclP		pb_decl;	RVarP		reg_var;	BitVecP		bit_vec;	MDeclP		m_decl;	PortDeclP	port_decl;}%start source_text/* keywords and tokens */%token <char_ptr> VL_ID		  /* verilog user defined identifier */%token <char_ptr> VL_BNUMBER	  /* binary integer */%token <char_ptr> VL_INUMBER	  /* decimal integer */%token <char_ptr> VL_ONUMBER	%token <char_ptr> VL_DNUMBER%token <char_ptr> VL_HNUMBER%token <real> VL_RNUMBER	  /* real */%token VL_STRING                  /* string quoted by "" */%token VL_ALLPATH                 /* *> */%token VL_ALWAYS                  /* always */%token VL_AND                     /* and */%token VL_ASSIGN                  /* assign */%token VL_BEGIN                   /* begin */%token VL_BUF                     /* buf */%token VL_BUFIF0                  /* bufif0 */%token VL_BUFIF1                  /* bufif1 */%token VL_CASE                    /* case */%token VL_CASEX                   /* casex */%token VL_CASEZ                   /* casez */%token VL_CMOS                    /* cmos */%token VL_CONDITIONAL             /* ?: */%token VL_DEASSIGN                /* deassign */%token VL_DEFAULT                 /* default */%token VL_DEFPARAM                /* defparam */%token VL_DISABLE                 /* disable */%token VL_ELSE                    /* else */%token VL_EDGE                    /* edge */%token VL_END                     /* end */%token VL_ENDCASE                 /* endcase */%token VL_ENDMODULE               /* endmodule */%token VL_ENDFUNCTION             /* endfunction */%token VL_ENDPRIMITIVE            /* endprimitive */%token VL_ENDSPECIFY              /* endspecify */%token VL_ENDTABLE                /* endtable */%token VL_ENDTASK                 /* endtask */%token VL_EVENT                   /* event */%token VL_FOR                     /* for */%token VL_FOREVER                 /* forever */%token VL_FORK                    /* fork */%token VL_FUNCTION                /* function */%token VL_GEQ                     /* >= */%token VL_HIGHZ0                  /* highz0 */%token VL_HIGHZ1                  /* highz1 */%token VL_IF                      /* if */%token VL_INITIAL                 /* initial */%token VL_INOUT                   /* inout */%token VL_INPUT                   /* input */%token VL_INTEGER                 /* integer */%token VL_JOIN                    /* join */%token VL_LARGE                   /* large */%token VL_LEADTO                  /* => */%token VL_LEQ                     /* =< */%token VL_LOGAND                  /* && */%token VL_CASEEQUALITY            /* === */%token VL_CASEINEQUALITY          /* !== */%token VL_LOGNAND                 /* ~& */%token VL_LOGNOR                  /* ~| */%token VL_LOGOR                   /* || */%token VL_LOGXNOR                 /* ~^ or ^~ */%token VL_LOGEQUALITY             /* == */%token VL_LOGINEQUALITY           /* != */%token VL_LSHIFT                  /* << */%token VL_MACROMODULE             /* macromodule */%token VL_MEDIUM                  /* medium */%token VL_MODULE                  /* module */%token VL_NAND                    /* nand */%token VL_NBASSIGN                /* <= non-blocking assignment */%token VL_NEGEDGE                 /* negedge */%token VL_NMOS                    /* nmos */%token VL_NOR                     /* nor */%token VL_NOT                     /* not */%token VL_NOTIF0                  /* notif0 */%token VL_NOTIF1                  /* notif1 */%token VL_OR                      /* or */%token VL_OUTPUT                  /* output */%token VL_PARAMETER               /* parameter */%token VL_PMOS                    /* pmos */%token VL_POSEDGE                 /* posedge */%token VL_PRIMITIVE               /* primitive */%token VL_PULL0                   /* pull0 */%token VL_PULL1                   /* pull1 */%token VL_PULLUP                  /* pullup */%token VL_PULLDOWN                /* pulldown */%token VL_RCMOS                   /* rcmos */%token VL_REAL                    /* real */%token VL_REG                     /* reg */%token VL_REPEAT                  /* repeat */%token VL_RIGHTARROW              /* -> */%token VL_RNMOS                   /* rnmos */%token VL_RPMOS                   /* rpmos */%token VL_RSHIFT                  /* >> */%token VL_RTRAN                   /* rtran */%token VL_RTRANIF0                /* rtranif0 */%token VL_RTRANIF1                /* rtranif1 */%token VL_SCALARED                /* scalared */%token VL_SMALL                   /* small */%token VL_SPECIFY                 /* specify */%token VL_SPECPARAM               /* secparam */%token VL_STRONG0                 /* strong0 */%token VL_STRONG1                 /* strong1 */%token VL_SUPPLY0                 /* supply0 */%token VL_SUPPLY1                 /* supply1 */%token VL_SWIRE                   /* swire */%token VL_TABLE                   /* table */%token VL_TASK                    /* task */%token VL_TIME                    /* time */%token VL_TRAN                    /* tran */%token VL_TRANIF0                 /* tranif0 */%token VL_TRANIF1                 /* tranif1 */%token VL_TRI                     /* tri */%token VL_TRI0                    /* tri0 */%token VL_TRI1                    /* tri1 */%token VL_TRIAND                  /* triand */%token VL_TRIOR                   /* trior */%token VL_TRIREG                  /* trireg */%token VL_VECTORED                /* vectored */%token VL_WAIT                    /* wait */%token VL_WAND                    /* wand */%token VL_WEAK0                   /* weak0 */%token VL_WEAK1                   /* weak1 */%token VL_WHILE                   /* while */%token VL_WIRE                    /* wire */%token VL_WOR                     /* wor */%token VL_XNOR                    /* xnor */%token VL_XOR                     /* xor */%token VL_sysSETUP                /* $setup */%token VL_sysID                   /* $... */%right VL_CONDITIONAL%right '?' ':'%left VL_OR%left VL_LOGOR%left VL_LOGAND%left '|'%left '&' '^' VL_LOGXNOR%left VL_LOGEQUALITY VL_LOGINEQUALITY VL_CASEEQUALITY VL_CASEINEQUALITY%left '<' VL_LEQ '>' VL_GEQ VL_NBASSIGN%left VL_LSHIFT VL_RSHIFT%left '+' '-'%left '*' '/' '%'%right '~' '!' VL_UNARYOPERATOR%type <char_ptr>	name_of_variable%type <list>		list_of_variables%type <char_ptr>	identifier%type <char_ptr>	primary%type <char_ptr>	constant_expression%type <char_ptr>	expression%type <char_ptr>	range_opt%type <char_ptr>	range%type <io_decl>		input_declaration%type <io_decl>		output_declaration%type <io_decl>		inout_declaration%type <m_decl>		module_declaration%type <m_item>		module_item%type <list>		module_item_opt%type <module>		module%type <list>		parameters_declaration%type <p_decl>		parameter_declaration%type <list> 		list_of_parameter_declaration%type <char_ptr>	lvalue%type <char_ptr>	assignment%type <char_ptr> 	list_of_parameters_opt%type <char_ptr> 	list_of_expressions%type <pb_decl>		always_statement%type <pb_decl>		guarded_always_statement%type <pb_decl>		initial_statement%type <pb_decl>		task_declaration%type <pb_decl>		assign_declaration%type <list>		expressions%type <char_ptr>	delay_control%type <char_ptr>	event_control%type <char_ptr>	event_expression%type <char_ptr>	scalar_event_expression%type <char_ptr>	name_of_memory%type <char_ptr>	name_of_register%type <reg_var>		register_variable%type <list> 		list_of_register_variables%type <bit_vec>		net_declaration%type <bit_vec>		reg_declaration%type <list>		ports%type <list>		list_of_ports_opt%type <port_decl>	port	%%source_text:	/* empty */	| source_text module	{	}	;module:	VL_MODULE VL_ID list_of_ports_opt ';' module_item_opt VL_ENDMODULE	{		$$=new Module($2);		while(!$5->empty()){			MItemP tmp=(MItemP)$5->remove();			/*			if(tmp->tip==IO)				$$->addIO(tmp->value);			if(tmp->tip==PAR)				$$->addPar(tmp->value);			if(tmp->tip==INIT)				$$->addProc(tmp->value);			*/			switch(tmp->tip)			{				case IO:					$$->addIO(tmp->value);					break;				case PAR:					//$$->addPar(tmp->value);					//break;					{					List *ltmp=(List*)tmp->value;					while(!ltmp->empty()){						PDeclP ptmp=(PDeclP)ltmp->remove();						$$->addPar(ptmp);					}					}				case ALW:				case INIT:				case ASSIGN:						$$->addProc(tmp->value);					break;				case TASK:					$$->addTask(tmp->value);					break;					case NET:				case REG:					//BitVecP t=(BitVecP)tmp->value;					//t->toVHDL(stdout);					$$->addNet(tmp->value);					break;				case MODULE:					$$->addModule(tmp->value);					break;			}		}		$$->shift_l = shift_l;		$$->shift_r = shift_r;		$$->unary_or = unary_or;		$$->unary_and = unary_and;		$$->unary_nor = unary_nor;		$$->unary_nand = unary_nand;		$$->unary_xor = unary_xor;		$$->unary_nxor = unary_nxor;		$$->toVHDL(output);			}	;list_of_ports_opt:	/* empty */	{		fprintf(debug,"list_of_ports_opt: /* empty */\n");		$$=new List();	}	|	 '(' ports ')'	{		fprintf(debug,"list_of_ports_opt: '(' ports ')'\n");		$$=$2;	}	;ports:	port	{		fprintf(debug,"ports: port\n");		$$=new List();		$$->add($1);			}	| ports ',' port	{		fprintf(debug,"ports: ports ',' port\n");		$1->add($3);		$$=$1;	}	;port:	/* empty */	{		$$=(PortDeclP)calloc(1,sizeof(PortDecl));		$$->signal=NULL;		$$->var=NULL;	}	|	lvalue	{		$$=(PortDeclP)calloc(1,sizeof(PortDecl));		fprintf(debug,"port: port_expression_opt\n");		$$->var=$1;		$$->signal=NULL;	}	| '.' VL_ID  '(' lvalue ')'	{		$$=(PortDeclP)calloc(1,sizeof(PortDecl));		fprintf(debug,"port: .VL_ID ports not implemented\n");		$$->var=$4;		$$->signal=$2;	}	;/**************EOP**************/name_of_variable	: VL_ID	{	};module_item_opt:	/*empty*/		{		$$=new List();	}	| module_item_opt module_item	{		//if($1==NULL)$1=new List;		/*if($2->tip==REG)		{			BitVecP tmp=(BitVecP)$2->value;			tmp->toVHDL(stdout);		}*/		$1->add((void*)$2);		$$=$1;	}	;module_item	: parameters_declaration          {		fprintf(debug,"module_item: parameter_declaration\n");		$$=(MItemP)calloc(1,sizeof(MItem));		$$->tip=PAR;		$$->value=(void*)$1;          }	| input_declaration          {		fprintf(debug,"module_item: input_declaration\n");		$$=(MItemP)calloc(1,sizeof(MItem));		$$->tip=IO;		$$->value=(void*)$1;          }	| output_declaration          {		fprintf(debug,"module_item: output_declaration\n");		$$=(MItemP)calloc(1,sizeof(MItem));		$$->tip=IO;		$$->value=(void*)$1;          }	| inout_declaration          {		fprintf(debug,"module_item: inout_declaration\n");		$$=(MItemP)calloc(1,sizeof(MItem));		$$->tip=IO;		$$->value=(void*)$1;          }	| net_declaration          {		fprintf(debug,"module_item: net_declaration\n");		$$=(MItemP)calloc(1,sizeof(MItem));		$$->tip=NET;		$$->value=(void*)$1;          }	| reg_declaration          {		fprintf(debug,"module_item: reg_declaration\n");		$$=(MItemP)calloc(1,sizeof(MItem));		$$->tip=REG;		$$->value=(void*)$1;		/*$1->toVHDL(stdout);*/          }	| module_declaration	  {		fprintf(debug,"module_declaration: \n");		$$=(MItemP)calloc(1,sizeof(MItem));		$$->tip=MODULE;		$$->value=$1;	  }	| initial_statement          {		fprintf(debug,"module_item: initial_statement\n");		$$=(MItemP)calloc(1,sizeof(MItem));		$$->tip=INIT;		$$->value=$1;          }	| always_statement          {		fprintf(debug,"module_item: always_statement\n");		$$=(MItemP)calloc(1,sizeof(MItem));		$$->tip=ALW;		$$->value=(void*)$1;          }		| guarded_always_statement	  {		fprintf(debug,"module_item: always_statement\n");		$$=(MItemP)calloc(1,sizeof(MItem));		$$->tip=ALW;		$$->value=(void*)$1;	  }	| task_declaration	  {		fprintf(debug,"module_item: task_declaration\n");		$$=(MItemP)calloc(1,sizeof(MItem));		$$->tip = TASK;		$$->value = $1;	  }	| assign_declaration	{		fprintf(debug,"module_item: assign\n");		$$=(MItemP)calloc(1,sizeof(MItem));		$$->tip = ASSIGN;		$$->value = $1;	  }	;assign_declaration	: VL_ASSIGN	{		fprintf(debug, "VL_ASSIGN\n");		$$=(PBDeclP)calloc(1,sizeof(PBDecl));		$$->file_name=beginproc();		fprintf(fp,"process begin\nloop\n"); 		buggy=$$;		t->inc();	}	statement	{		$$=(PBDeclP)buggy;		fprintf(debug,"assign_declaration: statement\n");		t->dec();		fprintf(fp,"end loop;\nend process;\n"); 		endproc();	}

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